XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 11

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

The optional weak-keeper circuit is connected to each out-
put. When selected, this circuit monitors the voltage on the
pad and weakly drives the pin High or Low. If the pin is con-
nected to a multiple-source signal, the weak-keeper holds
the signal in its last state if all drivers are disabled. Maintain-
ing a valid logic level in this way eliminates bus chatter.
Pull-up or pull-down resistors override the weak-keeper cir-
cuit.
Table 9: LVTTL and LVCMOS Programmable Currents (Sink and Source)
Figure 7
tions. HSTL can sink current up to 48 mA. (HSTL IV)
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Virtex-II
devices use two memory cells to control the configuration of
an I/O as an input. This is to reduce the probability of an I/O
configured as an input from flipping to an output when sub-
jected to a single event upset (SEU) in space applications.
Prior to configuration, all outputs not involved in configura-
tion are forced into their high-impedance state. The
pull-down resistors and the weak-keeper circuits are inac-
tive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
driven High, which disables the pull-up resistors on user I/O
DS122 (v1.1) January 7, 2004
Product Specification
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
SelectI/O-Ultra
Figure 7: SSTL or HSTL SelectI/O-Ultra Standards
shows the SSTL2, SSTL3, and HSTL configura-
OBUF
R
V CCO
2 mA
2 mA
2 mA
2 mA
2 mA
V REF
Clamp
Diode
4 mA
4 mA
4 mA
4 mA
4 mA
Programmable Current (Worst-Case Guaranteed Minimum)
V CCAUX = 3.3V
V CCINT = 1.5V
DS031_24_100900
PAD
6 mA
6 mA
6 mA
6 mA
6 mA
www.xilinx.com
1-800-255-7778
LVTTL sinks and sources current up to 24 mA. The current
is programmable for LVTTL and LVCMOS SelectI/O-Ultra
standards (see
trols for each output driver minimize bus transients. For
LVDCI and LVDCI_DV2 standards, drive strength and
slew-rate controls are not available.
pins. When HSWAP_EN is driven Low, the pull-up resistors
are activated on user I/O pins.
All Virtex-II IOBs support IEEE 1149.1 compatible bound-
ary-scan testing.
Input Path
The Virtex-II IOB input path routes input signals directly to
internal logic and/or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II device, and when
used, ensures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V
constraints on which standards can be used in the same
bank. See
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output and/or the 3-state
signal can be routed to the buffer directly from the internal
logic or through an output/3-state flip-flop or latch, or
through the DDR output/3-state registers.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most sig-
naling standards, the output High voltage depends on an
externally supplied V
imposes constraints on which standards can be used in the
same bank. See
I/O Banking
Some of the I/O standards described above require V
and V
8 mA
8 mA
8 mA
8 mA
8 mA
REF
QPro Virtex-II 1.5V Military QML Platform FPGAs
voltages. These voltages are externally supplied
I/O Banking
Table
I/O Banking
12 mA
12 mA
12 mA
12 mA
12 mA
REF
CCO
9). Drive-strength and slew-rate con-
. The need to supply V
description below.
voltage. The need to supply V
description below.
16 mA
16 mA
16 mA
16 mA
16 mA
REF
24 mA
24 mA
24 mA
n/a
n/a
imposes
CCO
CCO
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