XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 27

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

Table 17: Virtex-II Logic Resources Available in All CLBs
18 Kbit Block SelectRAM Resources
Introduction
Virtex-II devices incorporate large amounts of 18 Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an 18
Kbit true dual-port RAM with two independently clocked and
independently controlled synchronous ports that access a
common storage area. Both ports are functionally identical.
CLK, EN, WE, and SSR polarities are defined through con-
figuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for writes) and Data/parity
data outputs (for reads).
Operation is synchronous. The block SelectRAM behaves
like a register. Control, address, and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in
Table 18: Dual- and Single-Port Configurations
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18 Kbit memory locations in any of the 2K x 9-bit,
DS122 (v1.1) January 7, 2004
Product Specification
Notes:
1.
XQ2V1000
XQ2V3000
XQ2V6000
Device
The carry chains and SOP chains can be split or cascaded.
16K x 1 bit
8K x 2 bits
4K x 4 bits
R
CLB Array:
Column
40 x 32
64 x 56
96 x 88
Row x
Number
14,336
33,792
Slices
5,120
of
512 x 36 bits
1K x 18 bits
2K x 9 bits
Number
10,240
28,672
67,584
LUTs
of
Table
www.xilinx.com
1-800-255-7778
SelectRAM or Shift
18.
Max Distributed
Register (bits)
1,081,344
163,840
458,752
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of 9-bit, 18-bit,
and 36-bit widths is the ability to store a parity bit for every
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in
bus widths are identical.
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM has
access to a common 18 Kbit memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Figure 30: 18 Kbit Block SelectRAM Memory in
QPro Virtex-II 1.5V Military QML Platform FPGAs
Flip-Flops
Number
Figure
10,240
28,672
67,584
DI
DIP
ADDR
WE
EN
SSR
CLK
18 Kbit Block SelectRAM
of
Single-Port Mode
30. Input data bus and output data
Carry Chains
Number
112
176
64
of
DOP
DO
DS031_10_071602
(1)
Chains
Number
of SOP
128
192
80
(1)
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