XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 30

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports
with the control signals described in
inputs including the clock have an optional inversion.
Table 21: Control Functions
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
30
Control Signal
SSR
CLK
WE
EN
Enable affects Read, Write, Set, Reset
Set DO register to SRVAL (attribute)
Read and Write Clock
RAM Contents
Data_out
Write Enable
Address
Data_in
Data_in
Function
CLK
WE
Table
Figure 34: NO_CHANGE Mode
21. All control
DI
New
Old
aa
Internal
Memory
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Last Read Cycle Content (no change)
DO
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
number of CLBs in a column divided by four. Column loca-
tions are shown in
Table 22: SelectRAM Memory Floor Plan
XQ2V1000
XQ2V3000
XQ2V6000
Device
No change during write
New
Columns
Table
DS031_12_102000
4
6
6
22.
Per Column
DS122 (v1.1) January 7, 2004
SelectRAM Blocks
10
16
24
Product Specification
Total
144
40
96
R