XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 62

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
Clock Distribution Switching Characteristics
Table 48: Clock Distribution Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see
worst-case. Precise values are provided by the timing analyzer.
Table 49: CLB Switching Characteristics
62
Global Clock Buffer I input to O output
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
FXINA or FXINB inputs to Y output via MUXFX
FXINA input to FX output via MUXFX
FXINB input to FX output via MUXFX
SOPIN input to SOPOUT output via ORCY
Incremental delay routing through transparent latch to XQ/YQ
outputs
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times Before/After Clock CLK
BX/BY inputs
DY inputs
DX inputs
CE input
SR/BY inputs (synchronous)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
Minimum Pulse Width, SR/BY inputs
Delay from SR/BY inputs to XQ/YQ outputs (asynchronous)
Toggle Frequency (MHz) (for export control)
Description
Description
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1-800-255-7778
T
T
T
T
T
DXQK
CECK
SRCK/
DYCK
DICK
T
Symbol
T
T
T
SOPSOP
T
T
T
T
T
F
IFNCTL
T
T
T
INAFX
INBFX
T
CKLO
T
RPW
IF5X
IFXY
CKO
TOG
ILO
RQ
IF5
CH
CL
/T
/T
/T
/T
T
CKDI
CKDY
CKCE
SCKR
CKDX
Figure
Symbol
T
0.37/–0.09
0.37/–0.09
0.37/–0.09
0.24/–0.08
0.26/–0.03
GIO
49). The values listed below are
Min
0.77
0.77
0.77
-
-
-
-
-
-
-
-
-
-
-
-
DS122 (v1.1) January 7, 2004
Value
Product Specification
0.59
Max
0.44
0.72
0.95
0.45
0.32
0.32
0.44
0.51
0.57
0.68
1.34
650
-
-
-
-
-
-
-
-
Units
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R