XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 2

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
Table 1: Virtex-II Field-Programmable Gate Array Family Members
General Description
The Virtex-II family includes platform FPGAs developed for
high performance from low-density to high-density designs
that are based on IP cores and customized modules. The
family delivers complete solutions for telecommunication,
wireless, networking, video, and DSP applications, includ-
ing PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm/0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
8 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays. As shown in
Table
ranging from 1M to 6M system gates.
Packaging
Offerings include ball grid array (BGA) packages with
1.00 mm and 1.27 mm pitches. In addition to traditional
Architecture
Virtex-II Array Overview
Virtex-II devices are user-programmable gate arrays with
various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic
designs. As shown in
comprised of input/output blocks (IOBs) and internal config-
urable logic blocks (CLBs).
2
Notes:
1.
XQ2V1000
XQ2V3000
XQ2V6000
Device
See details in
1, the QPro Virtex-II family comprises three members,
System
Gates
Table 2
1M
3M
6M
Figure
, "
Maximum Number of User I/O Pads
Row x Col.
(1 CLB = 4 slices = Max 128 bits)
40 x 32
64 x 56
96 x 88
1, the programmable device is
Array
14,336
33,792
Slices
5,120
CLB
Distributed
RAM Kbits
Maximum
www.xilinx.com
1-800-255-7778
1,056
160
448
".
wire-bond interconnects, flip-chip interconnect is used in
some of the CGA offerings. The use of flip-chip interconnect
offers more I/Os than is possible in wire-bond versions of
the similar packages. Flip-chip construction offers the com-
bination of high pin count with high thermal capacity.
Table 2
The Virtex-II device/package combination table
page
device and package using wire-bond or flip-chip technology.
Table 2: Maximum Number of User I/O Pads
Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.
XQ2V1000
XQ2V3000
XQ2V6000
Multiplier
Blocks
5) details the maximum number of I/Os for each
144
40
96
Device
shows the maximum number of user I/Os available.
18 Kbit
Blocks
SelectRAM Blocks
144
40
96
Wire-Bond
Max RAM
(Kbits)
328
516
1,728
2,592
720
-
DS122 (v1.1) January 7, 2004
Product Specification
DCMs
12
12
8
Flip-Chip
824
(Table 5
-
-
Max I/O
Pads
1,104
432
720
(1)
on
R