XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 77

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

Table 74: QPro Virtex-II Pin Definitions (Continued)
DS122 (v1.1) January 7, 2004
Product Specification
Notes:
1.
PROG_B
DONE
M2, M1, M0
HSWAP_EN
TCK
TDI
TDO
TMS
PWRDWN_B
Other Pins
DXN, DXP
V
RSVD
V
V
V
GND
BATT
CCO
CCAUX
CCINT
Pin Name
All dedicated pins (JTAG and configuration) are powered by V
R
Input
Input/Output
Input
Input
Input
Input
Output
Input
(unsupported)
N/A
Input
N/A
Input
Input
Input
Input
Direction
Input
Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
Configuration mode selection.
Enable I/O pullups during configuration.
Boundary Scan Clock.
Boundary Scan Data Input.
Boundary Scan Data Output.
Boundary Scan Mode Select.
Active Low power-down pin (unsupported). Driving this pin Low can adversely affect
device operation and configuration. PWRDWN_B is internally pulled High, which is its
default state. It does not require an external pull-up.
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
Decryptor key memory backup supply. (Do not connect if battery is not used.)
Reserved pin - do not connect.
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
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CCAUX
(independent of the bank V
QPro Virtex-II 1.5V Military QML Platform FPGAs
Description
CCO
voltage).
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