XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 29

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. “WRITE_FIRST”
2. “READ_FIRST”
DS122 (v1.1) January 7, 2004
Product Specification
The “WRITE_FIRST” option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in
The “READ_FIRST” option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
R
Figure
32.
RAM Contents
RAM Contents
Data_out
Data_out
Address
Address
Data_in
Data_in
Data_in
Data_in
CLK
CLK
WE
WE
Figure 32: WRITE_FIRST Mode
Figure 33: READ_FIRST Mode
DI
DI
New
New
Old
Old
aa
aa
Internal
Internal
Memory
Memory
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DO
3. “NO_CHANGE”
DO
memory also transfers the prior content of the memory
cell addressed into the data output registers DO, as
shown in
The “NO_CHANGE” option maintains the content of the
output registers, regardless of the write operation. The
clock edge during the write mode has no effect on the
content of the data output register DO. When the port is
configured as “NO_CHANGE”, only a read operation
loads a new value in the output register DO, as shown in
Figure
QPro Virtex-II 1.5V Military QML Platform FPGAs
34.
Prior stored data
Data_out = Data_in
New
New
New
Old
Figure
DS031_13_102000
DS031_14_102000
33.
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