XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 41

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

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Creating a Design
Creating Virtex-II designs is easy with Xilinx Integrated Syn-
thesis Environment (ISE) development systems, which sup-
port advanced design capabilities, including ProActive
Timing Closure, integrated logic analysis, and the fastest
place and route runtimes in the industry. ISE solutions
enable designers to get the performance they need, quickly
and easily.
As a result of the ongoing cooperative development efforts
between Xilinx and EDA Alliance partners, designers can
take advantage of the benefits provided by EDA technolo-
gies in the programmable logic design process. Xilinx devel-
opment systems are available in a number of easy to use
configurations, collectively known as the ISE Series.
ISE Alliance
The ISE Alliance solution is designed to plug and play within
an existing design environment. Built using industry stan-
dard data formats and netlists, these stable, flexible prod-
ucts enable Alliance EDA partners to deliver their best
design automation capabilities to Xilinx customers, along
with the time to market benefits of ProActive Timing Clo-
sure.
ISE Foundation
The ISE Foundation solution delivers the benefits of true
HDL-based design in a seamlessly integrated design envi-
ronment. An intuitive project navigator, as well as powerful
HDL design and two HDL synthesis tools, ensure that
high-quality results are achieved quickly and easily. The ISE
Foundation product includes:
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Design Flow
Virtex-II design flow proceeds as follows:
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DS122 (v1.1) January 7, 2004
Product Specification
output signals vertically to the adjacent slice. (See
CLB/Slice
One dedicated SOP chain per slice row (two per CLB
row) propagates ORCY output logic signals
horizontally to the adjacent slice. (See
Products.)
One dedicated shift chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See
State Diagram entry using Xilinx StateCAD
Automatic HDL Testbench generation using Xilinx
HDLBencher
HDL Simulation using ModelSim XE
Design Entry
Synthesis
Implementation
Verification
Shift Registers, page
R
Configurations.)
22.)
Sum of
www.xilinx.com
1-800-255-7778
Most programmable logic designers iterate through these
steps several times in the process of completing a design.
Design Entry
All Xilinx ISE development systems support the mainstream
EDA design entry capabilities, ranging from schematic
design to advanced HDL design methodologies. Given the
high densities of the Virtex-II family, designs are created
most efficiently using HDLs. To further improve their time to
market, many Xilinx customers employ incremental, modu-
lar, and Intellectual Property (IP) design techniques. When
properly used, these techniques further accelerate the logic
design process.
To enable designers to leverage existing investments in
EDA tools and to ensure high-performance design flows,
Xilinx jointly develops tools with leading EDA vendors,
including:
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Complete information on Alliance Series partners and their
associated design flows is available at
on the Xilinx Alliance Series web page.
The ISE Foundation product offers schematic entry and
HDL design capabilities as part of an integrated design
solution, enabling one-stop shopping. These capabilities
are powerful, easy to use, and they support the full portfolio
of Xilinx programmable logic devices. HDL design capabil-
ities include a color-coded HDL editor with integrated lan-
guage templates, state diagram entry, and Core generation
capabilities.
Synthesis
The ISE Alliance product is engineered to support
advanced design flows with the industry's best synthesis
tools. Advanced design methodologies include:
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The ISE Foundation product seamlessly integrates synthe-
sis capabilities purchased directly from Exemplar, Synop-
sys, and Synplicity. In addition, it includes the capabilities of
Xilinx Synthesis Technology.
A benefit of having two seamlessly integrated synthesis
engines within an ISE design flow is the ability to apply alter-
native sets of optimization techniques on designs, helping
to ensure that designers can meet even the toughest timing
requirements.
Aldec
Cadence
Exemplar
Mentor Graphics
Model Technology
Synopsys
Synplicity
Physical Synthesis
Incremental synthesis
RTL floorplanning
Direct physical mapping
QPro Virtex-II 1.5V Military QML Platform FPGAs
http://www.xilinx.com
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