XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 66

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
Block SelectRAM Switching Characteristics
Table 54: Block SelectRAM Switching Characteristics
TBUF Switching Characteristics
Table 55: TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Table 56: JTAG Test Access Port Switching Characteristics
66
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
ADDR inputs
DIN inputs
EN input
RST input
WEN input
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Combinatorial Delays
IN input to OUT output
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Description
Description
Description
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T
T
T
T
T
BWCK
BDCK
BRCK
BACK
BECK
Symbol
T
T
T
BPWH
BPWL
BCKO
/T
/T
/T
/T
/T
BCKA
BCKD
BCKE
BCKR
BCKW
T
T
Symbol
Symbol
T
TCKTDO
TCKTAP
T
F
TAPTK
T
T
OFF
TCK
1.20/–0.58
1.65/–0.90
0.72/–0.25
ON
0.36/ 0.00
0.36/ 0.00
IO
Min
1.48
1.48
-
Min
Min
5.5
0.0
DS122 (v1.1) January 7, 2004
-
-
-
-
-
2.65
Min
Product Specification
-
-
-
-
-
-
-
Max
10.0
Max
0.58
0.55
0.55
33
-
-
Units
Units
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R