XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 55

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in
Table 44: IOB Output Switching Characteristics
DS122 (v1.1) January 7, 2004
Product Specification
Notes:
1.
Propagation Delays
O input to Pad
O input to Pad via transparent latch
3-State Delays
T input to Pad high-impedance
T input to valid data on Pad
T input to Pad high-impedance via transparent latch
T input to valid data on Pad via transparent latch
GTS to Pad high-impedance
Sequential Delays
Clock CLK to Pad
Clock CLK to Pad high-impedance (synchronous)
Clock CLK to valid data on Pad (synchronous)
Setup and Hold Times Before/After Clock CLK
O input
OCE input
SR input (OFF)
3
3
3
Set/Reset Delays
SR input to Pad (asynchronous)
SR input to Pad high-impedance (asynchronous)
SR input to valid data on Pad (asynchronous)
GSR to Pad
–
–
–
State Setup Times, T input
State Setup Times, TCE input
State Setup Times, SR input (TFF)
The 3-state turn-off delays should not be adjusted.
R
Description
(1)
(1)
IOB Output Switching Characteristics Standard Adjustments, page
(1)
(1)
(1)
www.xilinx.com
1-800-255-7778
T
T
T
T
IOOCECK
IOSRCKO
IOTCECK
IOSRCKT
T
T
IOOCK
IOTCK
T
T
T
T
T
T
T
Symbol
QPro Virtex-II 1.5V Military QML Platform FPGAs
T
T
T
T
T
IOTLPON
IOTLPHZ
T
IOCKON
IOSRON
IOGSRQ
IOCKHZ
IOSRHZ
T
IOOLP
IOTHZ
IOTON
IOCKP
IOSRP
IOOP
GTS
/T
/T
/T
/T
/T
/T
IOCKO
IOCKOCE
IOCKOSR
IOCKT
IOCKTCE
IOCKTSR
0.39/–0.11
0.24/–0.08
0.34/–0.07
0.35/–0.08
0.24/–0.08
0.34/–0.07
Min
Max
1.74
2.11
0.64
1.67
1.01
2.04
5.98
2.15
1.20
2.22
2.98
1.92
2.95
6.88
56.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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