XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 12

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in
bank has multiple V
nected to the same voltage. This voltage is determined by
the output standards in use.
Some input standards require a user-supplied threshold
voltage (V
configured as V
I/O pins in the bank assume this role.
V
consequently only one V
each bank. However, for correct operation, all V
the bank must be connected to the external reference volt-
age source.
The V
device pinout tables. Within a given package, the number of
12
Figure 8: Virtex-II I/O Banks: Top View for Wire-Bond
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Figure 9: Virtex-II I/O Banks: Top View for Flip-Chip
pins within a bank are interconnected internally, and
CCO
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and the V
), and certain user-I/O pins are automatically
Packages (CS, FG, & BG)
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Packages (FF & BF)
inputs. Approximately one in six of the
Bank 1
CCO
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Bank 4
Bank 0
Bank 5
pins for each bank appear in the
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pins, all of which must be con-
Figure 8
voltage can be used within
Bank 0
Bank 5
Bank 1
Bank 4
ug002_c2_014_112900
and
ds031_66_112900
Figure
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9. Each
pins in
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1-800-255-7778
V
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V
nected to the V
smaller devices, some V
not connect within the package. These unconnected pins
can be left unconnected externally, or, if necessary, they can
be connected to V
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bidirectional standards in the same bank:
1. Combining output standards only. Output standards
2. Combining input standards only. Input standards
3. Combining input standards and output standards.
4. Combining bidirectional standards with input or
5. Additional rules for combining DCI I/O standards.
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with the same output V
combined in the same bank.
Compatible example:
Incompatible example:
with the same input V
can be combined in the same bank.
Compatible example:
Incompatible example:
Incompatible example:
Input standards and output standards with the same
input V
combined in the same bank.
Compatible example:
Incompatible example:
output standards. When combining bidirectional I/O
with other standards, make sure the bidirectional
standard can meet rules 1 through 3 above.
a. No more than one Single Termination type (input or
b. No more than one Split Termination type (input or
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and V
SSTL2_I and LVDS_25_DCI outputs
SSTL2_I (output V
LVCMOS33 (output V
LVCMOS15 and HSTL_IV inputs
LVCMOS15 (input V
LVCMOS18 (input V
HSTL_I_DCI_18 (V
HSTL_IV_DCI_18 (V
LVDS_25 output and HSTL_I input
LVDS_25 output (output V
HSTL_I_DCI_18 input (input V
output) is allowed in the same bank.
Incompatible example:
output) is allowed in the same bank.
pins for the largest device anticipated must be con-
CCO
HSTL_IV_DCI input and HSTL_III_DCI input
CCO
and output V
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pins can vary depending on the size of
CCO
voltage and are not used for I/O. In
to permit migration to a larger device.
CCO
CCO
CCO
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CCO
CCO
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CCO
CCO
CCO
pins used in larger devices do
= 2.5V) and
= 0.9V) and
and input V
= 1.5V) and
= 1.8V) inputs
= 1.1V) inputs
requirement can be
= 3.3V) outputs
CCO
DS122 (v1.1) January 7, 2004
requirement can be
CCO
= 2.5V) and
Product Specification
= 1.8V)
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requirements
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pins
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R