XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 28

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
Table 19
Ports A and B.
Table 19: Dual-Port Mode Configurations
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kbit block is accessi-
ble from Port A or B. If both ports are configured in either
16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations, the
16 Kbit block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18 Kbit
memory block and the other port having access to a 16 Kbit
subset of the memory block equal to 16 Kbits.
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in
inputs and outputs and are independently clocked.
28
Figure 31: 18 Kbit Block SelectRAM in Dual-Port Mode
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
illustrates the different configurations available on
Figure
DIB
DIPA
ADDRA
WEA
ENA
SSRA
DIPB
ADDRB
WEB
ENB
SSRB
DIA
512 x 36
512 x 36
CLKA
CLKB
16K x 1
16K x 1
1K x 18
1K x 18
18 Kbit Block SelectRAM
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
31. The two ports have independent
512 x 36
DOPA
DOPB
16K x 1
1K x 18
1K x 18
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
DOA
DOB
DS031_11_071602
www.xilinx.com
1-800-255-7778
512 x 36
16K x 1
1K x 18
4K x 4
8K x 2
2K x 9
4K x 4
2K x 9
Port Aspect Ratios
Table 20
18 Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
Table 20: 18 Kbit Block SelectRAM Port Aspect Ratio
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully syn-
chronous. An address is presented, and the read operation
is enabled by control signals WEA and WEB in addition to
ENA or ENB. Then, depending on clock polarity, a rising or
falling clock edge causes the stored data to be loaded into
output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.
Width
18
36
1
2
4
9
shows the depth and the width aspect ratios for the
512 x 36
16,384
Depth
16K x 1
1K x 18
8,192
4,096
2,048
1,024
2K x 9
8K x 2
4K x 4
512
Address Bus
ADDR[13:0]
ADDR[12:0]
ADDR[11:0]
ADDR[10:0]
ADDR[9:0]
ADDR[8:0]
512 x 36
16K x 1
1K x 18
8K x 2
DS122 (v1.1) January 7, 2004
DATA[15:0]
DATA[31:0]
Data Bus
DATA[1:0]
DATA[3:0]
DATA[7:0]
DATA[0]
Product Specification
512 x 36
16K x 1
Parity Bus
Parity[1:0]
Parity[3:0]
Parity[0]
N/A
N/A
N/A
R