XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 34

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
Each global clock buffer can be driven by either the clock
pad to distribute a clock directly to the device, or the Digital
Clock Manager (DCM), discussed in
ager (DCM), page
driven by local interconnects. The DCM has clock output(s)
that can be connected to global clock buffer inputs, as
shown in
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks).
Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock distri-
34
Figure 40: Virtex-II Clock Distribution Configurations
Figure
Clock Distribution
Buffer
Clock
Clock
Pad
40.
I
0
36. Each global clock buffer can also be
NW
SW
8 BUFGMUX
16 Clocks
8 BUFGMUX
Clock Distribution
Digital Clock Man-
CLKOUT
CLKIN
Buffer
DS031_43_101000
DCM
Clock
Clock
Pad
Figure 42: Virtex-II Clock Distribution
I
0
SE
NE
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NW
SW
bution detail of the device prior to pin-locking and floorplan-
ning (see the Virtex-II User Guide,
Figure 42
In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.
To reduce power consumption, any unused clock branches
remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to
multiplex between two independent clock inputs (BUFG-
MUX).
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in
The Virtex-II global clock buffer BUFG can also be config-
ured as a clock enable/disable circuit
a two-input clock multiplexer
description of these two options is provided below. Each of
them can be used in either of two modes, selected by con-
figuration: rising clock edge or falling clock edge.
8
8
8 BUFGMUX
8 BUFGMUX
16 Clocks
Figure
shows clock distribution in Virtex-II devices.
Figure 41: Virtex-II BUFG Function
41.
I
8
8
BUFG
DS031_61_101200
DS031_45_120200
DS122 (v1.1) January 7, 2004
(Figure
UG002
O
8 max
SE
(Figure
NE
Product Specification
44). A functional
).
43), as well as
R