XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 8

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
Table 7: Supported Differential Signal I/O Standards
All of the user IOBs have fixed-clamp diodes to V
ground. As outputs, these IOBs are not compatible or com-
pliant with 5V I/O standards. As inputs, these IOBs are not
normally 5V tolerant, but can be used with 5V I/O standards
when external current-limiting resistors are used. For more
details, see the “5V Tolerant I/Os” Tech Topic at
http://www.xilinx.com
Table 8
trolled Impedance. See
(DCI), page
8
LVPECL_33
LDT_25
LVDS_33
LVDS_25
LVDSEXT_33
LVDSEXT_25
BLVDS_25
ULVDS_25
I/O Standard
lists supported I/O standards with Digitally Con-
OCK1
OCK2
OCK1
OCK2
Reg
Reg
Reg
Reg
13.
Figure 3: Virtex-II IOB Block
Output
DDR mux
DDR mux
V
3.3
2.5
3.3
2.5
3.3
2.5
2.5
2.5
CCO
3-State
Output
.
Digitally Controlled Impedance
Input
V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
CCO
IOB
Input
V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF
490 mV to 1.22V
ICK1
ICK2
Reg
Reg
Input
0.430 - 0.670
0.250 - 0.400
0.250 - 0.400
0.330 - 0.700
0.330 - 0.700
0.250 - 0.450
0.430 - 0.670
PAD
DS031_29_100900
Output
V
CCO
OD
and to
www.xilinx.com
1-800-255-7778
Table 8: Supported DCI I/O Standards
Logic Resources
IOB blocks include six storage elements, as shown in
Figure
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in
and 3-state data signals, each being alternately clocked out.
Notes:
1.
2.
LVDCI_33
LVDCI_DV2_33
LVDCI_25
LVDCI_DV2_25
LVDCI_18
LVDCI_DV2_18
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half
of the reference resistors.
These are SSTL compatible.
Standard
3.
I/O
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
Output
Figure
V
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
CCO
4. There are two input, output,
Input
V
N/A
N/A
N/A
N/A
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
2.5
2.5
3.3
3.3
CCO
DS122 (v1.1) January 7, 2004
Product Specification
Input
V
0.75
0.75
1.25
1.25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
1.0
0.9
0.9
0.9
0.9
1.1
1.1
1.5
1.5
REF
Termination
Series
Series
Series
Series
Series
Series
Series
Series
Single
Single
Single
Single
Single
Single
Type
Split
Split
Split
Split
Split
Split
Split
Split
R