XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 60

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

QPro Virtex-II 1.5V Military QML Platform FPGAs
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 46
ing Input standard adjustments (see
Table 46: Input Delay Measurement Methodology
60
Notes:
1.
2.
3.
4.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI-X
GTL
GTLP
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
SSTL3
Class I & II
SSTL2
Class I & II
AGP-2X
LVDS25
LVDS33
LVDSEXT25
LVDSEXT33
ULVDS25
LDT25
LVPECL
Standard
Input waveform switches between V
Measurements are made at typical, minimum, and maximum V
values. Reported delays reflect worst case of these measurements.
V
Guide
Input voltage level from which measurement starts.
Note that this is an input voltage reference that bears no relation to
the V
Figure
REF
REF
values listed are typical. See
shows the test setup parameters used for measur-
for min/max specifications.
51.
/ V
MEAS
V
V
(0.2
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
0.6 – 0.125
V
V
V
V
V
V
parameters found in IBIS models and/or noted in
REF
REF
1.6 – 0.3
REF
REF
REF
REF
REF
REF
V
V
REF
x
L
0
0
0
0
0
V
– 1.00
– 0.75
(1)
Per PCI-X Specification
– 0.2
– 0.2
– 0.5
– 0.5
– 0.5
– 0.5
CCO
Per PCI Specification
Per PCI Specification
–
)
V
V
(0.2
1.2 + 0.125
1.2 + 0.125
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
0.6 + 0.125
Virtex-II Platform FPGA User
V
V
V
V
V
V
L
REF
REF
1.6 + 0.3
and V
REF
REF
REF
REF
REF
REF
V
V
REF
x
3.0
3.3
2.5
1.8
1.5
H
Table 43, page
V
+ 1.00
+ 0.75
(1)
+ 0.2
+ 0.2
+ 0.5
+ 0.5
+ 0.5
+ 0.5
CCO
H
+
.
)
V
V
V
V
V
V
V
V
V
V
1.65
1.25
0.75
MEAS
(3,4)
1.4
0.9
1.2
1.2
1.2
1.2
0.6
0.6
1.6
REF
REF
REF
REF
REF
REF
REF
REF
REF
53).
V
Spec
AGP
0.80
0.75
0.75
0.90
0.90
1.25
www.xilinx.com
(2,4)
Per
1-800-255-7778
1.0
1.5
REF
REF
–
–
–
–
–
–
–
–
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pf) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See
The propagation delay of the 4" trace is characterized sep-
arately and subtracted from the final measurement, and is
therefore not included in the generalized test setup shown in
Figure
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at
inx.com/support/sw_ibis.htm.) Parameters V
C
I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:
1. Simulate the output driver of choice into the generalized
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
REF
test setup, using values from
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(Table
delay (clock-to-input) of the PCB trace.
, and V
51.
FPGA Output
Virtex-II Platform FPGA User Guide
45) to yield the actual worst-case propagation
Figure 51: Generalized Test Setup
MEAS
fully describe the test conditions for each
V
MEAS
MEAS
REF
R
C
(probe capacitance)
.
.
REF
REF
DS122 (v1.1) January 7, 2004
V
(voltage level at which
delay measurement is taken)
Table
MEAS
Product Specification
47.
http://support.xil-
ds083-3_06a_092503
REF
for details.)
, R
REF
R
,