XQ2V3000 Xilinx, XQ2V3000 Datasheet - Page 63

• Manufacturer Part Number: XQ2V3000
• Description: QPro Virtex-II 1.5V Military QML Platform FPGAs
• Manufacturer: Xilinx

CLB Distributed RAM Switching Characteristics
Table 50: CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Table 51: CLB Shift Register Switching Characteristics
DS122 (v1.1) January 7, 2004
Product Specification
Sequential Delays
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
F/G address inputs
SR input (WS)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
Sequential Delays
Clock CLK to X/Y outputs
Clock CLK to X/Y outputs
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
SR input (WS)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
R
Description
Description
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1-800-255-7778
T
SRLDS
T
WSS
QPro Virtex-II 1.5V Military QML Platform FPGAs
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
REGXB
REGYB
WES
REG32
REGF5
T
Symbol
T
CKSH
SRPH
SRPL
SHCKO16
SHCKO32
SHCKOF5
REG
DS
T
AS
T
/T
/T
T
WPH
WPL
WC
SRLDH
WSH
/T
/T
/T
AH
DH
WEH
0.67/–0.11
0.53/–0.01
0.50/ 0.00
0.67/–0.09
0.24/–0.08
Min
0.72
0.72
1.44
0.72
0.72
Min
-
-
-
-
-
-
-
-
-
Max
2.05
2.49
2.23
Max
2.92
3.35
2.82
2.75
2.43
3.09
-
-
-
-
-
-
-
-
-
-
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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