PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 162
![MODULE PROC PIC18F4685](/photos/8/96/89696/pcm18xt0_sml.jpg)
PCM18XT0
Manufacturer Part Number
PCM18XT0
Description
MODULE PROC PIC18F4685
Manufacturer
Microchip Technology
Datasheet
1.PCM18XT0.pdf
(484 pages)
Specifications of PCM18XT0
Accessory Type
Processor Module
Product
Microcontroller Modules
Core Processor
PIC18F4685
Lead Free Status / RoHS Status
Not applicable / Not applicable
For Use With/related Products
ICE2000
For Use With
ICE2000 - EMULATOR MPLAB-ICE 2000 POD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not applicable / Not applicable
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- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
14.1
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
FIGURE 14-1:
FIGURE 14-2:
DS39761C-page 162
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Timer3 Operation
T1OSI
T1OSI
CCP1/ECCP1 Special Event Trigger
CCP1/ECCP1 Special Event Trigger
Timer1 Oscillator
Timer1 Oscillator
TIMER3 BLOCK DIAGRAM
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1OSCEN
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
T1OSCEN
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
(1)
(1)
TCCPx
TCCPx
TMR3CS
TMR3CS
F
Internal
Clock
Clock
Internal
F
OSC
OSC
/4
/4
1
0
1
0
Clear TMR3
Timer1 clock input
Clear TMR3
Prescaler
Prescaler
1, 2, 4, 8
1, 2, 4, 8
cycle (F
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator if enabled.
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pins become inputs when the Timer1 oscillator
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
2
2
OSC
TMR3L
TMR3L
/4). When the bit is set, Timer3 increments
8
8
Synchronize
Synchronize
Sleep Input
Sleep Input
High Byte
TMR3H
Detect
Detect
TMR3
High Byte
8
TMR3
© 2009 Microchip Technology Inc.
8
8
1
0
1
0
Set
TMR3IF
on Overflow
Read TMR1L
Write TMR1L
Internal Data Bus
Set
TMR3IF
on Overflow
Timer3
On/Off
Timer3
On/Off
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