PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 178

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

PIC18F2682/2685/4682/4685
16.4.2
The PWM duty cycle is specified by writing to the
ECCPR1L register and to the ECCP1CON<5:4> bits.
Up to 10-bit resolution is available. The ECCPR1L
contains the eight MSbs and the ECCP1CON<5:4>
contains the two LSbs. This 10-bit value is represented
by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle
is calculated by the following equation.
EQUATION 16-2:
ECCPR1L and ECCP1CON<5:4> can be written to at
any time, but the duty cycle value is not copied into
ECCPR1H until a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
ECCPR1H is a read-only register.
The ECCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the ECCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the ECCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
TABLE 16-2:
DS39761C-page 178
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM Duty Cycle = (ECCPR1L:ECCP1CON<5:4> •
PWM Frequency
PWM DUTY CYCLE
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
T
OSC
• (TMR2 Prescale Value)
2.44 kHz
FFh
16
10
9.77 kHz
FFh
10
4
39.06 kHz
EQUATION 16-3:
16.4.3
The EPWM1M1:EPWM1M0 bits in the ECCP1CON
register allow one of four configurations:
• Single Output
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 16.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
Note:
FFh
10
1
PWM Resolution (max) =
If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
PWM OUTPUT CONFIGURATIONS
156.25 kHz
3Fh
1
8
© 2009 Microchip Technology Inc.
312.50 kHz
1Fh
log
1
7
(
log(2)
F
F
PWM
OSC
416.67 kHz
)
bits
6.58
17h
1