PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 284

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

PIC18F2682/2685/4682/4685
23.2.2
This section describes the dedicated CAN Transmit
Buffer registers and their associated control registers.
REGISTER 23-5:
DS39761C-page 284
Mode 0
Mode 1,2
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
2:
3:
This bit is automatically cleared when TXREQ is set.
While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in software while the bit is
set will request a message abort.
These bits define the order in which transmit buffers will be transferred. They do not alter the CAN
message identifier.
DEDICATED CAN TRANSMIT
BUFFER REGISTERS
bit 7
TXBIF: Transmit Buffer Interrupt Flag bit
1 = Transmit buffer has completed transmission of message and may be reloaded
0 = Transmit buffer has not completed transmission of a message
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.
0 = Automatically cleared when the message is successfully sent
Unimplemented: Read as ‘0’
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
TXBIF
TXBIF
R/C-0
R/C-0
TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 ≤ n ≤ 2]
TXABT
TXABT
R-0
R-0
(1)
(1)
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
TXLARB
TXLARB
R-0
R-0
(2)
(1)
(1)
(3)
(1)
TXERR
TXERR
R-0
R-0
(1)
(1)
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXREQ
TXREQ
R/W-0
R/W-0
(2)
(2)
U-0
U-0
—
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
TXPRI1
TXPRI1
R/W-0
R/W-0
(3)
(3)
TXPRI0
TXPRI0
R/W-0
R/W-0
bit 0
(3)
(3)