PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 42

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

PIC18F2682/2685/4682/4685
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
• The primary clock source is not any of the LP, XT,
TABLE 3-2:
DS39761C-page 42
Note 1:
is not stopped
HS or HSPLL modes
Primary Device Clock
T1OSC or INTRC
2:
3:
4:
5:
(PRI_IDLE mode)
Before Wake-up
Clock Source
(Sleep mode)
INTOSC
In this instance, refers specifically to the 31 kHz INTRC clock source.
T
with any other required delays (see Section 3.4 “Idle Modes”).
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
T
also designated as T
Execution continues during T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
CSD
OST
None
(parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
is the Oscillator Start-up Timer (parameter 32). t
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(3)
(1)
PLL
.
IOBST
After Wake-up
Clock Source
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
INTRC
INTRC
INTRC
INTRC
EC, RC
EC, RC
EC, RC
EC, RC
HSPLL
HSPLL
HSPLL
HSPLL
(parameter 39), the INTOSC stabilization period.
(1)
(1)
(1)
(1)
(3)
(3)
(3)
(3)
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval
T
leaving the Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
rc
is the PLL Lock-out Timer (parameter F12); it is
following the wake event is still required when
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
T
IOBST
IOBST
None
CSD
CSD
CSD
CSD
OST
OST
OST
+ t
+ t
+ t
(2)
(4)
(2)
(4)
(2)
(4)
(2)
rc
(5)
rc
rc
(5)
(4)
(4)
(4)
© 2009 Microchip Technology Inc.
Clock Ready Status
Bit (OSCCON)
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
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