PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 257

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

19.6
Figure 19-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 19-4 shows the operation of the A/D converter
after
ACQT2:ACQT0 bits are set to ‘010’ and a 4 T
acquisition time is selected before the conversion
starts.
FIGURE 19-3:
FIGURE 19-4:
© 2009 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
the
T
CY
Set GO/DONE bit
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
1
- T
GO/DONE
T
AD
ACQT
Acquisition
Conversion starts
Automatic
2
T
Time
AD
Cycles
1 T
A/D CONVERSION T
A/D CONVERSION T
3
AD
b9
bit
2 T
4
has
AD
b8
Conversion starts
(Holding capacitor is disconnected)
3 T
1
been
AD
b7
4 T
b9
2
set,
PIC18F2682/2685/4682/4685
AD
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
b8
3
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
the
AD
AD
b5
6 T
b7
4
AD
b4
7 T
T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the
last
registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
5
b6
AD
AD
Note:
b3
AD
Cycles
8
b5
wait is required before the next acquisition can
value
6
conversion
T
AD
b2
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
b4
7
written
AD
b1
10
b3
8
T
AD
sample.
ACQ
b0
ACQ
11
to
b2
9
= 0)
= 4 T
the
10
This
b1
AD
ADRESH:ADRESL
DS39761C-page 257
)
b0
11
means
the