PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 47

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

4.5
PIC18F2682/2685/4682/4685
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.1
The Power-up Timer (PWRT) of PIC18F2682/2685/
4682/4685 devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 μs = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
4.5.2
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
TABLE 4-2:
© 2009 Microchip Technology Inc.
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1:
Configuration
Oscillator
2:
Device Reset Timers
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2 ms is the nominal time required for the PLL to lock.
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP TIMER
(OST)
TIME-OUT IN VARIOUS SITUATIONS
66 ms
66 ms
(1)
devices
PWRTEN = 0
+ 1024 T
(1)
66 ms
66 ms
66 ms
+ 1024 T
Power-up
OSC
(1)
(1)
(1)
incorporate
PIC18F2682/2685/4682/4685
+ 2 ms
OSC
(2)
(2)
and Brown-out
4.5.3
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (T
the oscillator start-up time-out.
4.5.4
On power-up, the time-out sequence is as follows:
1.
2.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also apply
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
1024 T
PWRTEN = 1
After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
Then, the OST is activated.
1024 T
OSC
—
—
—
PLL LOCK TIME-OUT
TIME-OUT SEQUENCE
+ 2 ms
OSC
(2)
PLL
) is typically 2 ms and follows
Power-Managed Mode
1024 T
1024 T
Exit From
DS39761C-page 47
OSC
—
—
—
+ 2 ms
OSC
(2)