PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 45

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

4.2
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18F2682/2685/4682/4685 devices, the MCLR
input can be disabled with the MCLRE Configuration
bit. When MCLR is disabled, the pin becomes a digital
input. See Section 10.5 “PORTE, TRISE and LATE
Registers” for more information.
4.3
A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
V
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to V
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V
time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
© 2009 Microchip Technology Inc.
DD
DD
is adequate for operation.
is specified (parameter D004). For a slow rise
condition),
Master Clear Reset (MCLR)
Power-on Reset (POR)
DD
rises above a certain threshold. This
device
operating
DD
parameters
. This will
PIC18F2682/2685/4682/4685
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
FIGURE 4-2:
Note 1: External Power-on Reset circuit is required
V
2: R < 40 kΩ is recommended to make sure that
3: R1 ≥ 1 kΩ will limit any current flowing into
DD
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
MCLR from external capacitor C, in the event
of MCLR/V
static
Overstress (EOS).
V
DD
R
C
Discharge
PP
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
pin breakdown, due to Electro-
DD
R1
power-up slope is too slow.
powers down.
(ESD)
DD
MCLR
PIC18FXXXX
POWER-UP)
DS39761C-page 45
or
Electrical