MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 129

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Remember that the SRAM cannot be accessed by the on-chip DMAs. The on-chip system
configuration allows concurrent core and DMA execution where the core can execute code
out of internal SRAM or cache during DMA access.
The ColdFire processor or an external emulator using the debug module can perform these
initialization functions.
4.5.1 SRAM Initialization Code
The code segment below initializes the SRAM using RAMBAR0. The code sets the base
address of the SRAM at 0x2000_0000 and then initializes the RAM to zeros.
RAMBASE
RAMVALID
move.l
movec.l
The following loop initializes the entire SRAM to zero:
lea.l
move.l
SRAM_INIT_LOOP:
clr.l
subq.l
bne.b
The following function copies the number of bytesToMove from the source (*src) to the
processor’s local RAM at an offset relative to the SRAM base address defined by
destinationOffset. The bytesToMove must be a multiple of 16. For best performance, source
and destination SRAM addresses should be line-aligned (0-modulo-16).
; copyToCpuRam (*src, destinationOffset, bytesToMove)
RAMBASE
RAMFLAGS
; stack arguments and locations
2. Read the source data and write it to the SRAM. Various instructions support this
3. After the data is loaded into the SRAM, it may be appropriate to revise the
function, including memory-to-memory move instructions and the move multiple
instruction (MOVEM). MOVEM is optimized to generate line-sized burst fetches on
line-aligned addresses, so it generally provides maximum performance.
RAMBAR attribute bits, including the write-protect and address space mask fields.
If the SRAM contains instructions, RAMBAR[D/I] must be set to logically connect
the memory to the processor’s internal instruction bus.
lea.l
movem.l
EQU
EQU
#RAMBASE+RAMVALID,D0
D0, RAMBAR
RAMBASE,A0
#512,D0
(A0)+
#1,D0
SRAM_INIT_LOOP
EQU
EQU
-12(a7),a7
#0x1c,(a7)
0x20000000
0x00000035
0x20000000
0x00000035
0
Chapter 4. Local Memory
;set this variable to 0x20000000
;load RAMBASE + valid bit into D0
;load RAMBAR
;load pointer to SRAM
;load loop counter into D0
;clear 4 bytes of SRAM
;decrement loop counter
;exit if done; else continue looping
;SRAM base address
;RAMBAR valid + mask bits
;allocate temporary space
;store D2/D3/D4 registers
0
and enable SRAM
SRAM Initialization
4-5