MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 153

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 4-14 shows the two possible states for a cache line in write-through mode.
Table 4-7 describes data cache line transitions and the accesses that cause them.
Read
miss
Read hit
Write
miss
(copy-
back)
Write
miss
(write-
through)
Write hit
(copy-
back)
Access
WI3—CPU write miss
WI5—DCINVA
WI6—CPUSHL & DDPI
WI7—CPUSHL & DDPI
(C,W)I1 Read line from
(C,W)I2 Not possible.
CI3
WI3
CI4
Figure 4-14. Data Cache Line State Diagram—Write-Through Mode
Invalid (V = 0)
memory and update
cache;
supply data to
processor;
go to valid state.
Read line from
memory and update
cache;
write data to cache;
go to modified state.
Write data to
memory;
stay in invalid state.
Not possible.
Table 4-7. Data Cache Line State Transitions
Invalid
V = 0
Chapter 4. Local Memory
(C,W)V1 Read new line from
(C,W)V2 Supply data to processor;
CV3
WV3
CV4
WI1—CPU read miss
WV5—DCINVA
WV6—CPUSHL & DDPI
Valid (V = 1, M = 0)
memory and update
cache;
supply data to processor;
stay in valid state.
stay in valid state.
Read new line from
memory and update
cache;
write data to cache;
go to modified state.
Write data to memory;
stay in valid state.
Write data to cache;
go to modified state.
Current State
V = 1
Valid
WD3 Write data to memory;
CD1 Push modified line to
CD2 Supply data to processor;
CD3 Push modified line to
CD4 Write data to cache;
Cache Operation Summary
Modified (V = 1, M = 1)
buffer;
read new line from memory
and update cache;
supply data to processor;
write push buffer contents
to memory;
go to valid state.
stay in modified state.
buffer;
read new line from memory
and update cache;
write push buffer contents
to memory;
stay in modified state.
stay in modified state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
stay in modified state.
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL & DDPI
4-29