MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 169

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 5-10 describes BAAR fields
5.4.4 Configuration/Status Register (CSR)
The configuration/status register (CSR) defines the debug configuration for the processor
and memory subsystem and contains status information from the breakpoint logic.
1
2
DRc[4–0]
DRc[4–0]
CSR is write-only from the programming model. It can be read from and written to through the BDM port. CSR
is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through
the BDM port using the
Bit 7 is reserved for Motorola use and must be written as a zero.
Reset
Reset
Reset
Field
7
6–5
4–3
2–0
R/W
Field
Field MAP TRC EMU
R/W BAAR[R,SZ] are loaded directly from the BDM command; BAAR[TT,TM] can be programmed as debug
Bits
R/W R/W R/W R/W
1
control register 0x05 from the external development system. For compatibility with Rev. A, BAAR is loaded
each time AATR is written.
R
SZ
TT
TM
Name
31
15
0
R
7
30
14
0
BSTAT
Read/write
0 Write
1 Read
Size
00 Longword
01 Byte
10 Word
11 Reserved
Transfer type. See the TT definition in Table 5-7.
Transfer modifier. See the TM definition in Table 5-7.
0000
Figure 5-8. BDM Address Attribute Register (BAAR)
R
Figure 5-9. Configuration/Status Register (CSR)
29
13
0
RDMREG
6
28
12
Table 5-10. BAAR Field Descriptions
DDC
R/W
and
SZ
00
FOF TRG HALT BKPT
27
11
R
0
WDMREG
Chapter 5. Debug Support
5
.
UHE
R/W
26
10
R
0
0
commands.
25
R
0
9
BTB
R/W
4
00
0000_0101
24
R
0
8
Description
0x05
0x00
TT
—
23
R
0
7
2
3
NPL
R/W
22
0
6
0010
HRL
R
—
—
—
21
5
2
SSM
R/W
20
0
4
Programming Model
19
—
—
—
3
TM
1
BKD PCD IPW
—
—
18
2
—
—
—
—
—
17
1
0
5-13
R/W
16
0
0