MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 256

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupt Controller Registers
Table 9-6 shows the correlation between AVR[AVEC] and the external interrupts. Note that
an AVECn bit is valid only when the corresponding external interrupt request level is
enabled in the IRQPAR.
9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)
The interrupt pending register (IPR), Figure 9-4, makes visible the interrupt sources that
have an interrupt pending. The interrupt mask register (IMR), also shown in Figure 9-4, is
used to mask the internal and external interrupt sources.
An interrupt is masked by setting, and enabled by clearing, the corresponding IMR bit.
When a masked interrupt occurs, the corresponding IPR bit is still set, but no interrupt
request is passed to the core.
9-6
7–1
.
Bit
0
Autovector Interrupt Source
External interrupt request 1
External interrupt request 2
External interrupt request 3
External interrupt request 4
External interrupt request 5
External interrupt request 6
External interrupt request 7
Name
AVEC Autovector control. Determines whether the external interrupt at that level is autovectored.
BLK
0 Interrupting source returns vector during interrupt-acknowledge cycle.
1 SIM generates autovector during interrupt-acknowledge cycle.
Block address strobe (AS) for external AVEC access. Available for users who use AS as a global
chip select for peripherals and do not want to enable them during an AVEC cycle.
0 Do not block address strobe.
1 Block address strobe from asserting.
To mask interrupt sources, first set the core’s status register
interrupt mask level to that of the source being masked in the
IMR. Then, the IMR bit can be masked.
Table 9-6. Autovector Register Bit Assignments
Table 9-5. AVR Field Descriptions
MCF5407 User’s Manual
Autovector Register Bit Location
NOTE:
AVEC1
AVEC2
AVEC3
AVEC4
AVEC5
AVEC6
AVEC7
Description
Vector Offset
0x6C
0x7C
0x64
0x68
0x70
0x74
0x78