MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 164

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model
Two scenarios exist for data—0xFFFF_FFFF
Thus, a count of either nine or more sequential single 0xF values or five or more sequential
0xFF values signifies the HALT condition.
5.4 Programming Model
In addition to the existing BDM commands that provide access to the processor’s registers
and the memory subsystem, the debug module contains 19 registers to support the required
functionality. These registers are also accessible from the processor’s supervisor
programming model by executing the WDEBUG instruction. Thus, the breakpoint
hardware in the debug module can be accessed by the external development system using
the debug serial interface or by the operating system running on the processor core.
Software is responsible for guaranteeing that accesses to these resources are serialized and
logically consistent. Hardware provides a locking mechanism in the CSR to allow the
external development system to disable any attempted writes by the processor to the
breakpoint registers (setting CSR[IPW]). BDM commands must not be issued if the
MCF5407 is using the WDEBUG instruction to access debug module registers or the
resulting behavior is undefined.
These registers, shown in Figure 5-5, are treated as 32-bit quantities, regardless of the
number of implemented bits.
5-8
• A B marker occurs on the left nibble of PSTDDATA with the data of 0xFF
• A B marker occurs on the right nibble of PSTDDATA with the data of 0xFF
following:
PSTDDATA[7:0]
0xBF
0xFF
0xFF
0xFF
0xFX (X indicates that the next PST value is guaranteed to not be 0xF.)
following:
PSTDDATA[7:0]
0xYB
0xFF
0xFF
0xFF
0xFF
0xXY (X indicates the PST value is guaranteed not to be 0xF, and Y signifies a
PSTDDATA value that doesn’t affect the 0xFF count.)
MCF5407 User’s Manual