MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 269

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 11
Synchronous/Asynchronous DRAM
Controller Module
This chapter describes configuration and operation of the synchronous/asynchronous
DRAM controller component of the system integration module (SIM). It begins with a
general description and brief glossary, and includes a description of signals involved in
DRAM operations. The remainder of the chapter consists of the two following parts:
11.1 Overview
The DRAM controller module provides glueless integration of DRAM with the ColdFire
product. The key features of the DRAM controller include the following:
• Section 11.3, “Asynchronous Operation,” describes the programming model and
• Section 11.4, “Synchronous Operation,” describes the programming model and
• Support for two independent blocks of DRAM
• Interface to standard synchronous/asynchronous dynamic random access memory
• Programmable SRAS, SCAS, and refresh timing
• Support for page mode
• Support for 8-, 16-, and 32-bit wide DRAM blocks
• Support for synchronous and asynchronous DRAMs, including EDO DRAM,
signal timing for the four basic asynchronous modes.
— Non-page mode
— Burst page mode
— Continuous page mode
— Extended data-out mode
signal timing, as well as the command set required for synchronous operations. This
section also includes extensive examples the designer can follow to better
understand how to configure the DRAM controller for synchronous operations.
(ADRAM/SDRAM) components
SDRAM, and fast page mode
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
11-1