MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 318

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DMA Controller Module Programming Model
12-6
Channel
DMA
0
1
2
3
0x3CC
MBAR
Offset
0x30C
0x34C
0x38C
0x3C0
0x3C4
0x3C8
0x3D0
0x3D4
0x300
0x304
0x308
0x310
0x314
0x340
0x344
0x348
0x350
0x354
0x380
0x384
0x388
0x390
0x394
Table 12-3. Memory Map for DMA Controller Module Registers
External masters cannot access MCF5407 on-chip memories or
MBAR, but they can access DMA module registers.
DMA status register 0
DMA status register 1
DMA status register 2
DMA status register 3
DMA interrupt vector
DMA interrupt vector
DMA interrupt vector
DMA interrupt vector
register 0 (DIVR0)
register 1 (DIVR1)
register 2 (DIVR2)
register 3 (DIVR3)
(DSR0) [p. 12-10]
(DSR1) [p. 12-10]
(DSR2) [p. 12-10]
(DSR3) [p. 12-10]
Reserved
Reserved
Reserved
Reserved
[p. 12-11]
[p. 12-11]
[p. 12-11]
[p. 12-11]
[31:24]
MCF5407 User’s Manual
Destination address register 0 (DAR0) [p. 12-7]
Destination address register 1 (DAR1) [p. 12-7]
Destination address register 2 (DAR2) [p. 12-7]
Destination address register 3 (DAR3) [p. 12-7]
Source address register 0 (SAR0) [p. 12-7]
Source address register 1 (SAR1) [p. 12-7]
Source address register 2 (SAR2) [p. 12-7]
Source address register 3 (SAR3) [p. 12-7]
DMA control register 0 (DCR0) [p. 12-8]
DMA control register 1 (DCR1) [p. 12-8]
DMA control register 2 (DCR2) [p. 12-8]
DMA control register 3 (DCR3) [p. 12-8]
[23:16]
NOTE:
Byte count register 0 (BCR0) [p. 12-7]
Byte count register 1 (BCR1) [p. 12-7]
Byte count register 2 (BCR2) [p. 12-7]
Byte count register 3 (BCR3) [p. 12-7]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[15:8]
[7:0]