MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 523

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
MBAR
Offset
MBAR
Offset
0x08C
0x09C
0x0AC
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to
these reserved address spaces and reserved register bits have no effect.
MBAR
Offset
0x10C
0x0A0
0x0A4
0x0A8
0x0B0
0x0B4
0x0B8
0x080
0x084
0x088
0x090
0x094
0x098
0x100
0x104
0x108
0x110
0x114
Chip-select address register—bank 0 (CSAR0)
Chip-select address register—bank 1 (CSAR1)
Chip-select address register—bank 2 (CSAR2)
Chip-select address register—bank 3 (CSAR3)
Chip-select address register—bank 4 (CSAR4)
DRAM control register (DCR) [p. 11-3]
[31:24]
[31:24]
[31:24]
Table B-3. Chip-Select Registers (Continued)
Table B-4. DRAM Controller Registers
Reserved
Reserved
Reserved
Reserved
Reserved
[p. 10-6]
[p. 10-6]
[p. 10-6]
[p. 10-6]
[p. 10-6]
DRAM address and control register 0 (DACR0) [p. 11-3]
DRAM address and control register 1 (DACR1) [p. 11-3]
Appendix B. List of Memory Maps
Chip-select mask register—bank 0 (CSMR0) [p. 10-7]
Chip-select mask register—bank 1 (CSMR1) [p. 10-7]
Chip-select mask register—bank 2 (CSMR2) [p. 10-7]
Chip-select mask register—bank 3 (CSMR3) [p. 10-7]
Chip-select mask register—bank 4 (CSMR4) [p. 10-7]
DRAM mask register block 0 (DMR0) [p. 11-3]
DRAM mask register block 1 (DMR1) [p. 11-3]
1
1
1
1
1
[23:16]
[23:16]
[23:16]
Reserved
Chip-select control register—bank 0 (CSCR0)
Chip-select control register—bank 1 (CSCR1)
Chip-select control register—bank 2 (CSCR2)
Chip-select control register—bank 3 (CSCR3)
Chip-select control register—bank 4 (CSCR4)
[15:8]
[15:8]
[15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[p. 10-8]
[p. 10-8]
[p. 10-8]
[p. 10-8]
[p. 10-8]
1
1
1
1
1
[7:0]
[7:0]
[7:0]
B-3