MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 291

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

31–18
17–9
Bits
11.4.4 General Synchronous Operation Guidelines
To reduce system logic and to support a variety of SDRAM sizes, the DRAM controller
provides SDRAM control signals as well as a multiplexed row address and column address
to the SDRAM.
When SDRAM blocks are accessed, the DRAM controller can operate in either burst or
continuous page mode. The following sections describe the DRAM controller interface to
SDRAM, the supported bus transfers, and initialization.
11.4.4.1 Address Multiplexing
Table 11-6 shows the generic address multiplexing scheme for SDRAM configurations. All
possible address connection configurations can be derived from this table.
The following tables provide a more comprehensive, step-by-step way to determine the
correct address line connections for interfacing the MCF5407 to SDRAM. To use the
6–1
8
7
0
Name
BAM
AMx
WP
—
—
V
Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect to various
DRAM sizes. Mask bits need not be contiguous (see Section 11.5, “SDRAM Example.”)
0 The associated address bit is used in decoding the DRAM hit to a memory block.
1 The associated address bit is not used in the DRAM hit decode.
Reserved, should be cleared.
Write protect. Determines whether the associated block of DRAM is write protected.
0 Allow write accesses
1 Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an
Reserved, should be cleared.
Address modifier masks. Determine which accesses can occur in a given DRAM block.
0 Allow access type to hit in DRAM
1 Do not allow access type to hit in DRAM
Valid. Cleared at reset to ensure that the DRAM block is not erroneously decoded.
0 Do not decode DRAM accesses.
1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded.
address exception occurs. Write accesses to a write-protected DRAM region are compared in the
chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus
cycle is not acknowledged, an access exception occurs.
AM
SC
SD
UC
UD
Bit
C/I
CPU space/interrupt acknowledge
Alternate master
Supervisor code
Supervisor data
User code
User data
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Table 11-14. DMR0/DMR1 Field Descriptions
Associated Access Type
Description
MOVEC instruction or interrupt acknowledge cycle
External or DMA master
Any supervisor-only instruction access
Any data fetched during the instruction access
Any user instruction
Any user data
Access Definition
Synchronous Operation
11-23