MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 454

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Operation of External Master Transfers
shown in Figure 18-25, the MCF5407 continues to assert BD until the completion of the
bus cycle. If BG is negated by the end of the bus cycle, the MCF5407 negates BD. While
BG is asserted, BD remains asserted to indicate the MCF5407 is master, and it continuously
drives the address bus, attributes, and control signals.
In the second situation, the bus is granted to the MCF5407, but it does not have an internal
bus request pending, so it takes implicit bus mastership. The MCF5407 does not drive the
bus and does not assert BD if the bus has an implicit master. If an internal bus request is
generated, the MCF5407 assumes explicit bus mastership. If explicit mastership was
assumed because an internal request was generated, the MCF5407 immediately begins an
access and asserts BD.
In Figure 18-28, the external device is bus master during C1 and C2. During C3 the external
device releases control of the bus by asserting BG to the MCF5407. At this point, there is
an internal access pending so the MCF5407 asserts BD during C4 and begins the access.
Thus, the MCF5407 becomes the explicit external bus master. Also during C4, the external
device removes the grant from the MCF5407 by negating BG. As the current bus master,
the MCF5407 continues to assert BD until the current transfer completes. Because BG is
negated, the MCF5407 negates BD during C9 and three-states the external bus, thereby
returning external bus mastership to the external device.
18-26
s
SIZ[1:0], TM[2:0]
A[31:0], TT[1:0]
Figure 18-27. Two-Wire Bus Arbitration with Bus Request Asserted
CLKIN
D[31:0]
R/W
TIP
BG
BD
AS
TS
TA
C1
External Master
C2
MCF5407 User’s Manual
C3
C4
C5
C6
MCF5407
C7
C8
C9