MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 505

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

word-sized operands and position-independent code. Existing MCF5307 code is
completely upward compatible with the MCF5407. However, designers may incorporate
the instruction set additions and enhancements, especially when upgrading 68K code that
references 8- and 16-bit short operands.
The following list summarizes new and enhanced instructions of Rev B ISA:
Refer to Section 2.9, “ColdFire Instruction Set Architecture Enhancements” for details of
these additions and enhancements.
A.3 Enhanced Memories
With the introduction of a Harvard memory architecture in the Version 4 core design, the
MCF5407 has separate instruction and data caches. The 16-Kbyte instruction cache and
8-Kbyte data cache greatly improve performance on existing systems. On-chip RAMs are
also provided to work with the caches. For more details see, Chapter 4, “Local Memory”.
The MCF5307 configuration contains an 8-Kbyte unified cache with a 4-Kbyte SRAM.
Configuration registers for these memories include one cache control register (CACR), two
access control registers (ACR0 and ACR1), and one RAM base address register
(RAMBAR). With the enhanced memory sizes of the MCF5407, more configuration
registers have been provided. The new MOVEC register map for the MCF5407 memory
configuration registers is given in Table A-2.
• New instructions:
• Enhancements to existing Revision A instructions:
— INTOUCH loads instructions one cache block at a time for use with cache
— MOV3Q.L moves 3-bit immediate data to the destination location.
— MVS.{B,W} moves the sign-extended source operand to the destination register.
— MVZ.{B,W} zero-fills the source operand and moves it to the destination
— SATS.L updates bit 31 of the destination register depending on the CCR
— TAS.B tests and sets byte operand being addressed.
— Longword support for branch instructions (Bcc, BRA, BSR)
— Byte and word support for compare instructions (CMP, CMPI)
— Byte and longword support for MOVE where the source is of type #<data> and
locking.
register.
overflow bit.
the destination is of type d16(Ax); that is, move.b #<data>, d16(Ax)
Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407
Enhanced Memories
A-3