MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 168

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model
5.4.2 Address Breakpoint Registers (ABLR/ABLR1,
The address breakpoint low and high registers (ABLR, ABLR1, ABHR, and ABHR1),
Figure 5-7, define regions in the processor’s data address space that can be used as part of
the trigger. These register values are compared with the address for each transfer on the
processor’s high-speed local bus. TDR determines if the trigger is in the address in ABLR
or either inside or outside of the range bound by ABLR and ABHR. XTDR determines the
same for ABLR1 and ABHR1.
Table 5-8 describes ABLR and ABLR1 fields.
Table 5-9 describes ABHR and ABHR1 fields.
5.4.3 BDM Address Attribute Register (BAAR)
The BAAR defines the address space for memory-referencing BDM commands. See
Figure 5-8. The reset value of 0x5 sets supervisor data as the default address space.
5-12
DRc[4–0]
31–0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
31–0
Bits
Bits
Reset
Field
R/W ABHR and ABHR1 are accessible in supervisor mode as debug control registers 0x0C and 0x1C, using the
Figure 5-7. Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1)
Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range.
Name
Name
WDEBUG instruction and via the BDM port using the
ABLR and ABLR1 are accessible in supervisor mode as debug control register 0x0D and 0x1D, using the
WDEBUG instruction and via the BDM port using the
ABHR/ABHR1)
31
Breakpoints for specific addresses are programmed into ABLR or ABLR1.
Table 5-9. ABHR and ABHR1 Field Description
Table 5-8. ABLR and ABLR1 Field Description
0x0D (ABLR); 0x1D (ABLR1); 0x0C (ABHR); 0x1C (ABHR1)
MCF5407 User’s Manual
Address
Description
Description
—
RDMREG
WDMREG
and
command.
WDMREG
commands.
0