MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 532

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Glossary-2
F
E
H
Cache flush. An operation that removes from a cache any data from a
Cache line. The smallest unit of consecutive data or instructions that is stored
Caching-inhibited. A memory update policy in which the cache is bypassed
Cast outs. Cache lines that must be written to memory when a cache miss
Clear. To cause a bit or bit field to register a value of zero. See also Set.
Copyback. A cache memory update policy in which processor write cycles
Effective address (EA). The 32-bit address specified for an instruction.
Exception. A condition encountered by the processor that requires special,
Exception handler. A software routine that executes when an exception is
Fetch. The act of retrieving instructions from either the cache or main
Flush. An operation that causes a modified cache line to be invalidated and
Harvard architecture. An architectural model featuring separate caches for
system. Caches are coherent if a processor performing a read from
its cache is supplied with data corresponding to the most recent value
written to memory or to another processor’s cache.
specified address range. This operation ensures that any modified
data within the specified address range is written back to main
memory.
in a cache. For ColdFire processors a line consists of 16 bytes.
and the load or store is performed to or from main memory.
causes a cache line to be replaced.
are directly written only to the cache. External memory is updated
only indirectly, for example, when a modified cache line is cast out
to make room for newer data.
supervisor-level processing.
taken. Normally, the exception handler corrects the condition that
caused the exception, or performs some other meaningful task (that
may include aborting the program that caused the exception). The
address for each exception handler is identified by an exception
vector defined by the ColdFire architecture.
memory and making them available to the instruction unit.
the data to be written to memory.
instruction and data.
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