MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 174

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DRc[4–0]
Programming Model
5.4.7 Trigger Definition Register (TDR)
The TDR, shown in Table 5-13, configures the operation of the hardware breakpoint logic
that corresponds with the ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and
DBR/DBMR registers within the debug module. In conjunction with the XTDR and its
associated debug registers, TDR controls the actions taken under the defined conditions.
Breakpoint logic may be configured as one- or two-level triggers. TDR[31–16] and/or
XTDR[31–16] define second-level triggers and bits 15–0 define first-level triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Section 5.4.9, “Resulting Set of Possible Trigger Combinations,” describes how to handle
multiple breakpoint conditions.
Table 5-17 describes TDR fields.
5-18
Reset
Reset
Field
Field
R/W Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the
R/W Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the
BDM port using the
BDM port using the
31
15
TRC
—
30
14
The debug module has no hardware interlocks, so to prevent
spurious breakpoint triggers while the breakpoint registers are
being loaded, disable TDR and XTDR (by clearing
TDR[29,13] and XTDR[29,13]) before defining triggers.
EBL
EBL
29
13
Figure 5-13. Trigger Definition Register (TDR)
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
28
12
WDMREG
WDMREG
27
11
command.
command.
26
10
MCF5407 User’s Manual
25
0000_0000_0000_0000
0000_0000_0000_0000
9
NOTE:
Second-Level Triggers
First-Level Triggers
24
8
0x07
23
7
22
6
DI
DI
21
5
EAI EAR EAL EPC PCI
EAI EAR EAL EPC PCI
20
4
19
3
18
2
17
1
16
0