MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 462

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset Operation
18.10.1 Master Reset
To perform a master reset, an external device asserts RSTI. When power is applied to the
system, external circuitry should assert RSTI for a minimum of 16 CLKIN cycles after
EVcc and IVcc are within tolerance. Figure 18-33 is a functional timing diagram of the
master reset operation, showing relationships among E/IVcc, RSTI, mode selects, and bus
signals. CLKIN must be stable by the time E/IVcc reach the minimum operating
specification. See Section 20.1.1, “Supply Voltage Sequencing and Separation Cautions.”
CLKIN should start oscillating as E/IVcc are ramped up to clear out contention internal to
the MCF5407 caused by the random states of internal flip-flops on power up. RSTI is
internally synchronized for two CLKIN cycles before being used and must meet the
specified setup and hold times in relationship to CLKIN to be recognized.
During the master reset period, all signals capable of being three-stated are driven to a
high-impedance; all others are negated. When RSTI negates, all bus signals remain in a
high-impedance state until the MCF5407 is granted the bus and the core begins the first bus
cycle for reset exception processing. A master reset causes any bus cycle (including DRAM
refresh cycle) to terminate and initializes registers appropriately for a reset exception.
Note that during reset D[7:0] are sampled on the negating edge of RSTI for initial
MCF5407 configurations listed in Table 18-12.
18-34
EVCC, IVCC
Bus Signals
CLKIN
RSTO
D[7:0]
RSTI
BR
BD
Figure 18-33. Master Reset Timing
MCF5407 User’s Manual
>16 CLKIN cycles
50K CLKIN cycles
PLL lock time