PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet
PSB2115FV1.2D
Specifications of PSB2115FV1.2D
Related parts for PSB2115FV1.2D
PSB2115FV1.2D Summary of contents
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ICs for Communications ISDN PC Adapter Circuit IPAC PSB 2115 Version 1.1 Data Sheet 11. ...
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PSB 2115 Revision History: Previous Version: Preliminary Data Sheet 03.97 Page Page Subjects (major changes since last revision) (in previous (in new Version) Version) For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.4 S/T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.7.4 MONITOR Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.6.3.2 TE/LT-T Modes Transition Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 ...
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Table of Contents 4.2.24 XCCR - Transmit Channel Capacity Register (WRITE .235 4.2.25 RCCR - Receive Channel Capacity Register (WRITE ...
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Table of Contents 4.4 General IPAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 41: Timing Diagram for DMA-Transfers (slow) Transmit (n < 64, remainder of a long message Figure 42: Timing Diagram for DMA-Transfer (fast) Receive ( Figure 43: Timing Diagram for DMA-Transfers ...
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List of Figures Figure 78: IPAC Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 119:State Transition Diagram in TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . 311 Figure 120:State Diagram of the TE/LT-T Modes, Unconditional ...
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List of Tables Table 1: Programming of Timeslots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview The ISDN PC Adapter Circuit IPAC integrates all necessary functions for a host based ISDN access solution on a single chip. It includes the S-transceiver (Layer 1), an HDLC controller for the D-channel and two protocol controllers for ...
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ISDN PC Adapter Circuit IPAC Version 1.1 1.1 Features • Single chip host based ISDN solution • Integrates S-transceiver, D-channel, B-channel protocol controller • Replaces solutions based on ISAC-S TE PSB 2186 and HSCX-TE PSB 21525 • Easy adjustment of ...
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Logic Symbol The logic symbol shows all functions of the IPAC. It must be noted, that not all functions are available simultaneously, but depend on the selected mode. Pins which are marked with a “ * “ are multiplexed ...
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Pin Configuration Figure 2 shows the pin configuration for P-MQFP-64 and for P-TQFP-64 packages. VDD BCL / SCLK DU DD FSC DCL VSS MODE0 MODE1 / EAW ACL SDS AUX7 AUX6 AUX5 AUX4 AUX3 Figure 2 Pin Configuration Semiconductor ...
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Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) Microprocessor Interface 8 9 AD0-7 I D0...7 I A0- ...
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Pin No. Symbol Input (I) Output (O) 3 ALE I 2 INT OD 27 DRQTB O 28 DRQRB O Semiconductor Group Function Address Latch Enable A HIGH on this line indicates an address on the external address/data bus (multiplexed bus ...
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Pin No. Symbol Input (I) Output (O) 29 DACKA I 30 DACKB Auxiliary Interface 31 AUX0 I/O Semiconductor Group Function DMA Acknowledge (channel A/B) When LOW, this input signal from the DMA controller indicates to the IPAC, that the requested ...
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Pin No. Symbol Input (I) Output (O) 32 AUX1 I/O 33 AUX2 I/O Semiconductor Group Function Auxiliary Port 1 TE-Mode: DRQRA (output) DMA Request Receiver (channel A) The receiver of the IPAC requests DMA data transfer by activating this line. ...
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Pin No. Symbol Input (I) Output (O) 64 AUX3 I/O 63 AUX4 I/O 62 AUX5 I/O Semiconductor Group Function Auxiliary Port 3 TE-Mode: AUX3 (input/output) This pin is programmable as general input/output. The state of the pin can be read ...
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Pin No. Symbol Input (I) Output (O) 61 AUX6 I/O 60 AUX7 IOM-2 Interface 53 FSC I/O 54 DCL I I/O(OD I/O (OD) 50 BCL/ O SCLK Semiconductor Group Function Auxiliary Port 6/7 All Modes: INT0/1 ...
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Pin No. Symbol Input (I) Output (O) 59 SDS O Miscellaneous 34 RES I/O 35 AMODE I 56 MODE0 I 57 MODE1 I EAW I 58 ACL O 47 SX1 O 48 SX2 O Semiconductor Group Function Serial Data Strobe ...
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Pin No. Symbol Input (I) Output (O) 45 SR1 I 44 SR2 I 41 XTAL1 I 42 XTAL2 O 40 C768 Power Supply 1 VDD VDDA I 7 VSS ...
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Functional Block Diagram Figure 3 Block Diagram Semiconductor Group 26 PSB 2115 PSF 2115 Overview 11.97 ...
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System Integration The IPAC is suited for all host based applications. ISDN PC Adapter Card for S Interface An ISDN adapter card for built around the IPAC using a USB, PCI or PnP interface device depending ...
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ISDN PC Adapter Card for Interface An ISDN adapter card which supports both U and S interface may be realized using the IPAC together with the PSB 21910 IEC-Q TE (figure 5). The S interface may be ...
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ISDN Voice/Data Terminal Figure 6 shows a voice data terminal developed card, where the IPAC provides its functionality as data controller + S interface within a two chip solution. During ISDN calls the ARCOFI-SP PSB 2163 provides ...
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ISDN Stand-alone Terminal with POTS interface The IPAC (LT-T mode) can be integrated in a microcontroller based stand-alone terminal (figure 7) that is connected to the communications interface of a PC. The SICOFI2-TE PSB 2132 enables connection of analog terminals ...
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Multiline PC-Adapter Up to three S-interfaces can be combined using one IOM interface (figure 8). All three IPACs are configured for LT-T mode in different channels. The SCLK output is used for DCL clock and the FSC clock is generated ...
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Functional Description The ISDN PC Adapter Circuit IPAC replaces solutions which are based on ISAC-S TE PSB 2186 and HSCX-TE PSB 21525. Most of the functions of both devices are integrated on the IPAC with further modifications and improvements ...
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Transparent Mode 1 (MODEB: MDS1, MDS0, ADM = 101) Characteristics: address recognition high byte Only the high byte of a 2-byte address field will be compared. The whole frame except the first address byte will be stored in RFIFOB. ...
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Receive Data Flow The following figure gives an overview of the management of the received HDLC frames as affected by different operating modes. FLAG MDS1 MDS0 ADM MODE Non Auto/16 Non Auto/8 1 ...
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Transmit Data Flow Transparent frames can be transmitted as shown below. FLAG Transmit Transparent Frame (XTF) Figure 10 Transmit Data Flow of IPAC For transparent frames (command XTF via CMDRB register), the address and the control fields have to ...
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Serial Interface The two serial interfaces of the IPAC provide two fully independent channels for B- channel communication. 2.1.7.1 Clock Mode 5 (Time-Slots) This operating mode has been designed for application in time-slot oriented PCM systems well ...
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Register: TSAR TSAX FSC BCL SDS Figure 11 Location of Time-Slots Note: In extended transparent mode the width of the time-slots has The active time-slot can additionally be indicated by a programmable strobe signal SDS of which ...
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Data Encoding In the point-to-point configuration, the IPAC supports both NRZ and NRZI data encoding (selectable via CCR1 register). Figure 12 NRZ Encoding/NRZI Encoding During NRZI encoding, level changes are interpreted as log 0, and no changes in level ...
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Fully Transparent Transmission and Reception When programmed to the extended transparent mode via the MODEB register (MDS1, MDS0 = 11), each channel of the IPAC supports fully transparent data transmission and reception without HDLC framing overhead, i.e. without • ...
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Note: In DMA-mode the command XREP, XTF has to be written to CMDRB. 2.1.10 Continuous Transmission (DMA Mode only) If data transfer from system memory to the IPAC is done by DMA (DMA bit in XBCH set), the number of ...
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RME interrupt, and the – RAB bit in RSTA register is set! To distinguish between frames really aborted from the opposite station, the receive byte count (readable from RBCHB, RBCLB registers) exceeds the maximum receive length (via RL5 … ...
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D-Channel Operation 2.2.1 Layer-2 Functions for HDLC The D-Channel HDLC controller in the IPAC is responsible for the data link layer using HDLC/SDLC based protocols. The IPAC can be configured to support data link layer to a degree that ...
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There are 5 different operating modes which can be set via the MODED register: Auto Mode (MDS2, MDS1 = 00) Characteristics: – Full address recognition ( bytes). – Normal (mod 8) or extended (mod 128) control field format ...
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Transparent Mode 1 (MDS2, MDS1, MDS0 = 101). Characteristics: TEI recognition A comparison is performed only on the second byte after the opening flag, with TEI1, TEI2 and group TEI (FF H the (first byte of the) control field in ...
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Reception of Frames A 2x32-byte FIFO buffer (receive pools) is provided in the receive direction. The control of the data transfer between the CPU and the IPAC is handled via interrupts. There are two different interrupt indications concerned with ...
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Address Flag High Auto-Mode SAP1,SAP2 (U and I frames) FE,FC (Note 1) Non-Auto SAP1,SAP2 Mode FE,FC (Note 1) Transparent SAPR Mode 1 Transparent Mode 2 Transparent SAP1,SAP2 Mode 3 FE,FC Description of Symbols: Figure 15 Receive Data Flow Note 1: ...
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When 32 bytes of a message longer than that are stored in RFIFOD, the CPU is prompted to read out the data by an RPF interrupt. The CPU must handle this interrupt before more than 32 additional bytes are received, ...
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Information about the received frame is available for the P when the RME interrupt is generated, as shown in table 2. Table 2 Receive Information at RME Interrupt Information Register First byte after flag SAPR (SAPI of LAPD address field) ...
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Transmission of Frames byte FIFO buffer (transmit pools) is provided in the transmit direction. If the transmit pool is ready (which is true after an XPR interrupt or if the XFW bit in STARD is set), ...
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For transparent frames, the whole frame including address and control field must be written to the XFIFOD. The transmission of I frames is possible only if the IPAC is operating in the auto mode. The address and control field is ...
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If the IPAC is operating in the auto mode, the window size (= number of outstanding unacknowledged frames) is limited to 1; therefore an acknowledgment is expected for every I frame sent with an XIF command. The acknowledgment may be ...
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Control Procedures Control procedures describe the commands and messages required to control the IPAC PSB 2115 in different modes and situations. This chapter shows the user how to activate and deactivate the device under various circumstances. In order to ...
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Deactivation A deactivation of the S-interface can only be initiated by the exchange side (IPAC in LT-S mode possible to begin a deactivation process from all interim activation states, i.e. not only from the fully activated state. ...
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D-Channel Access Control D-channel access control was defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. Figure 18 illustrates that collisions are possible on the TIC- and the S-bus. Figure ...
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The TIC bus is used to control D-channel access on the IOM interface when more than one HDLC controller is connected. This configuration is illustrated in the above figure for TE1 where three ICCs are connected to one IOM-2 bus. ...
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IOM-2 bus. The TIC bus request remains unaffected (i.e. if access was granted the TIC address and BAC bit are activated). As soon as the S-bus D-channel is clear and the S/G bit was set back to ...
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TE may start transmission of an HDLC frame collision occurs, the TE immediately shall cease transmission, return to the D-channel monitoring state, and send 1s over the D-channel. 2.3.4.3 S-Bus D-channel ...
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Application 1. Priority Class 8/10 Selection with NT Initiated Activation TE IOM -2 C/I DC (1111b) C/I DI (1111b) C/I RSY (0100b) C/I AR (1000b) C/I AI (1100b) C/I AR8 (1000b transfer HDLC frame C/I AR10 (1001b) _ ...
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S-Bus D-Channel Control in LT-T In LT-T mode the IPAC is primarily considered point-to-point configuration. In these configurations no S-bus D-channel collision can occur, therefore the default setting after resetting the IPAC is transparent (IOM-2 ...
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Table 3 IPAC Configuration Settings in Intelligent NT Applications Functional Configuration Description Block Layer 1 Select LT-S mode Select IOM-2 channel 1 Activate NT state machine Map channels B1, B2 and D to IOM channel 0 Layer 2 Select TE ...
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NT D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The IPAC S-transceiver thus receives BAC = “1” (IOM-2 DU ...
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Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: • ...
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Figure 19 Data Flow for Collision Resolution Procedure in Intelligent NT Semiconductor Group Functional Description 63 PSB 2115 PSF 2115 11.97 ...
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The state machine for D-channel access in the intelligent NT describes four states and four types of conditions for state transition: States Ready The D-channel is transparent to the layer 1 (D device occupies the D-channel (BAC=1). The echo bits ...
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IOM -2 Interface Channel Switching In order to realize intelligent NT configurations the IPAC provides basic switching functions. These include: • Individual channel transfer from the selected (i.e. pin strapped) IOM-2 channel (channel IOM-2 channel ...
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The following four examples illustrate typical switching operations. Three of them are programmed in the “IOM-2 Channel” register, example No. 4 makes use of the “Loopback” register. All register bits related to the channel are set to ...
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Connection U-TE (B1) IPAC (LT- IOM -2 Reg. 4. Connection TE1 (B1) IPAC (LT-S) IB1 = IB2 = 1 B2 IB12 = 1 R (IOM -2 channel 1) Loopback Reg. Semiconductor ...
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S/T Interface 2.4.1 Operating Modes The S-transceiver supports terminal mode (TE), line termination subscriber side mode (LT-S) and line termination trunk side mode (LT-T). The selection is performed by two mode pins (see table 4), additionally the B-channel receive ...
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S/T-Interface Coding Transmission over the S/T-interface is performed at a rate of 192 kbit/s. Pseudo-ternary coding with 100 % pulse width is used (see following section). 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for ...
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Figure 23 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N – ...
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S/T-Interface Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer 1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Q- channel). The Q bits are defined to be ...
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In TE and LT-T mode the IPAC identifies the Q-bit position (after multi-frame synchronization has been established) by waiting for the F S/T-interface data stream (F the Q data will be inserted at the upstream (TE synchronization is not achieved ...
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Table 6 MON-8 “Write to Register” Structure 1. Byte MON-8 Table 7 MON-8 “Read Register Request” Structure 1. Byte MON-8 The response issued by the IPAC after having received a ...
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MON-8 Configuration Register In the configuration register the user programs the IPAC for different operational modes, and selects required S-bus features. The following paragraphs describe the application relevance of all individual configuration register bits. Address: 1h MFD 0 Value ...
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SQM Selects the SQ channel handling mode. In non-auto mode operation, the IPAC issues S1 and Q messages in the IOM-2 monitor channel only after a change has been detected. The S2 channel is not available in non-auto mode. In ...
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MON-8 Loop-Back Register The loop-back register controls all analog (S/T-interface) and digital (IOM-2 interface) loop-backs. Additionally the wake-up mode can be programmed. Address: 2h AST SB1 Value after Reset AST Asynchronous Timing. Defines the length of ...
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IB2 Close the loop-back for B2 channel close to the IOM-2 interface (i.e. loop- back S/T data). Transparent. IB1 and IB2 may be closed simultaneously. IB12 Exchange B1 and B2 channels. IB1 and/or IB2 need to be programmed also. Loops ...
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MON-8 IOM -2 Channel Register The features accessible via the IOM-2 Channel register allow to implement simple switching functions. These make the IPAC the ideal device for intelligent NT applications. Please refer also to the section “IOM-2 channel switching”. ...
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MON-8 SM/CI Register This multifeature register allows access to the C/I channel and controls the monitor time- out. Address: 4h CI3 CI2 Value after Reset contains the C/I code) H C/I Allows the user to access the ...
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Layer-1 Functions for the S/T Interface The common functions in all operating modes are: – line transceiver functions for the S/T interface according to the electrical specifications of CCITT I.430; – conversion of the frame structure between IOM and ...
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IPAC TR TE IPAC TR LT-T 1) The maximum line attenuation tolerated by the IPAC kHz. _ < < IPAC TE1 TE8 Figure 24 Wiring Configurations in User Premises ...
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Analog Functions For both receive and transmit direction, a 2:1 transformer is used to connect the ISAC- S transceiver to the 4 wire S/T interface (CONF:AMP=0 option, the receiver can also be operated with a 1:1 transformer ...
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IPAC 2.5 V (CONF : AMP = O) IPAC 2.5 V (CONF : AMP = 1) Figure 26 Equivalent Internal Circuits of Receiver and Transmitter Stages The transmitter of the PSB 2115 ...
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S/T Interface Circuitry 2.5.2.1 S/T Interface Pre-Filter Compensation To compensate for the extra delay introduced into the receive and transmit path by the external circuit, the delay of the transmit data can be reduced by 260 ns (i.e. two ...
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The following recommendations aim at achieving the highest possible device protection against overvoltages while still fulfilling the 96 kHz impedance tests. If the device is not used LT-T applications, the four diodes could be bridged and the ...
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Protection Circuit for Receivers Figure 28 illustrates the external circuitry used in combination with a symmetrical receiver. Protection of symmetrical receivers is rather comfortable. Note: Capacitors are optional for noise reduction ( pF) Figure 28 External Circuitry for ...
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Receiver Functions 2.5.3.1 Receiver Characteristics In order to additionally reduce the bit error rate in severe conditions, the IPAC performs oversampling of the received signal and uses majority decision logic. The receiver consists of a differential to single ended ...
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Figure 30 Receiver Thresholds The peak detector requires maximum reach the peak value while storing the peak level for at least 250 s (RC > 1 ms). The additional level detector for power up/down control works with ...
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S/T Transmitter Disable The transmitter of the S/T interface can be disabled by configuration (see figure 31). By default (SCFG:TXD=0) both the S/T receiver and transmitter are active, but in order to reduce power consumption, the transmitter can be ...
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Timing Recovery LT-S In LT-S mode, the 192-kHz transmit bit clock is synchronized to the IOM clock. In the receive direction two cases have to be distinguished depending on whether a bus or a point-to-point operation is programmed in ...
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TE and LT-T In TE/LT-T applications, the transmit and receive bit clocks are derived, with the help of the DPLL, from the S interface receive data stream. The received signal is sampled several times inside the derived receive clock period, ...
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Activation/Deactivation An incorporated finite state machine controls ISDN layer-1 activation/deactivation according to CCITT. Setting of the IPAC for CTS Test Procedures for Frame Alignment The IPAC needs to be programmed for multiframe operation with the Q-bits set to "1". ...
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Activation Indication via Pin ACL The activated state of the S-interface is directly indicated via pin ACL (Activation LED). An LED with pre-resistance may directly be connected to this pin and a low level is driven on ACL as ...
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Terminal Specific Functions (TE mode only) In addition to the standard functions supporting the ISDN basic access, the IPAC contains optional functions, useful in various terminal configurations. The terminal specific functions are enabled by setting bit TSF (STCR register) ...
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A reset signal is generated as a result of the expiration of the watchdog timer (indicated by the WOV interrupt status). Note: The watchdog timer is not running when the IPAC is in the power-down state (IOM not clocked). ...
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Test Functions 2.5.9.1 B-Channel Test Mode To provide for fast and efficient testing, the IPAC can be operated in the test mode by setting the TLP bit in the MODEB register. The serial data input and output (DU – ...
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S interface LT-T mode Test loop 3 is activated with the C/I channel command Activate Request Loop (ARL interface is not required since INFO3 is looped back internally ...
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Microprocessor Interface 2.6.1 Operation Modes The IPAC is programmed via an 8-bit parallel microprocessor interface. Easy and fast microprocessor access is provided by 8-bit address decoding on the chip. The IPAC provides three types of P buses (see table ...
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As a second option, the IPAC allows for indirect access of the registers (AMODE=1). Only the LSB of the address line is used to select either the ADDRESS register or the DATA register. The host writes the register address to ...
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Data Transfer Mode Data transfer between the system memory and the IPAC for both transmit and receive direction is controlled either by interrupts (Interrupt Mode), or independently from host interaction using the IPAC’s 4-channel DMA interface (DMA Mode). DMA ...
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Figure 39 IPAC Interrupt Status Registers Two interrupt indications can be read directly from the ISTA register and another six interrupt indications from separate interrupt status registers and extended interrupt registers for the B-channels (ISTAB, EXIRB, each for B-Channel A ...
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Table 11 Auxiliary Interface Interrupts Bit Register Interrupt INT0/1 ISTA External Interrupt 0/1 Table 12 D-Channel Interrupts Bit Register Interrupt ICD ISTA ISTA D-Channel EXD ISTA EXIR D-Channel Receive Interrupts: Bit Register Interrupt RPF ISTAD Receive Pool Full RME ISTAD ...
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Table 12 D-Channel Interrupts MOS EXIRD MONITOR Status SAW EXIRD Subscriber Awake WOV EXIRD Watchdog Timer Overflow Table 13 B-Channel Interrupts Bit Register Interrupt ICA/ ISTA ISTA B-Channel A/B ICB EXA/ ISTA EXIR B-Channel A/B EXB Receive Interrupts: Bit Register ...
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DMA Interface To support efficient data exchange between system memory and the FIFOs an additional DMA-interface is provided. The FIFOs have separate DMA-request lines for each direction (DRQRA/B for Receive FIFO, DRQTA/B for Transmit FIFO) and a common DMA-acknowledge ...
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Figure 41 Timing Diagram for DMA-Transfers (slow) Transmit (n < 64, remain- der of a long message receive direction the behavior of pin DRQR is implemented correspondingly bytes are transferred, pin DRQR is ...
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Figure 43 Timing Diagram for DMA-Transfers (slow) Receive ( Figure 44 Timing Diagram for DMA-Transfers (slow or fast) Receive ( 32) Generally it is the responsibility of the DMA-controller to perform the correct ...
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If a pulsed DACK-signal is used the DRQR/DRQT-signal will be deactivated with the rising edge of RD/WR-operation (n-1) but activated again with the following rising edge of DACK. With the next falling edge of DACK (DACK ‘n’) it will be ...
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FIFO Structure for B-Channels In both transmit and receive direction 128 byte deep FIFO’s are provided for the intermediate storage of B-Channel data between the serial interface and the CPU interface. The FIFO’s are divided into two halves of ...
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If frames longer than 128 bytes are received, the device will repeatedly prompt to read out 64 byte data blocks via interrupt. In the case of several shorter frames may be stored in the IPAC. If the ...
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Timer Modes The IPAC provides two timers which can be used for various purposes: TIMR1 - Timer 1 Register (Adr. A3 TIMR2 - Timer 2 Register (Adr. CC Timer 1 provides two modes of operation which can be selected ...
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S-frame has been received. A timer interrupt (ISTAD:TIN) is generated after the last retry. The procedure is stopped when either a TIN interrupt is generated or the TIMR1 register is written or when a positive or negative acknowledgement ...
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Software Reset The host can issue a reset command to the IPAC which has the same functionality as a hardware reset. In register C9h bit POTA2:SRES (Software Reset) is used to release the reset which has only effect on ...
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IOM -2 Interface ® 2.7.1 IOM -2 Frame Structure / Timing Modes The IOM generalization and enhancement of the IOM-1. While the basic frame structure is very similar, IOM-2 offers further capacity for the transfer of ...
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Non-TE timing mode This mode is used in LT-S and LT-T applications. The frame is a multiplex of eight IOM- 2 channels (figure 52), each channel has the structure as shown in figure 51. The IPAC is assigned to one ...
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TE Timing Mode The frame is composed of three channels (figure 53): • Channel 0 contains 144 kbit/s (for 2B+D) plus MONITOR and Command/Indication channels for the layer-1 device. • Channel 1 contains two 64-kbit/s intercommunication channels plus MONITOR and ...
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Strobe Signal A data strobe signal is generated with every 8-kHz frame active high for a duration of either bits (SCFG:TLEN) and its start position is programmable to one channels (SCFG:TSLT) ...
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IOM -2 Interface Connections Output Driver Selection FSC and DCL are push pull outputs (TE mode). The output type of the IOM datalines is selectable via bit CONF:ODS. ODS set to 0 selects open drain (reset value) and ...
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Figure 55 IOM-2 Direction Control Semiconductor Group Functional Description 118 PSB 2115 PSF 2115 11.97 ...
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Terminal Mode In TE mode the IOM-2 interface has the 12-byte frame structure consisting of channels 0, 1 and 2 (see figure 53): – DD carries the 2B+D channels from the S/T interface, and the MONITOR 0 and C/I 0 ...
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Figure 56 IOM-2 Data Ports DU/DD in Terminal Mode (MODE0=0) Semiconductor Group Functional Description 120 PSB 2115 PSF 2115 11.97 ...
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Non-Terminal Mode / LT-T Mode Outside the selected 4-byte subscriber channel, both DU and DD are inactive. The reset value for the active channel can be selected by pin strapping (in LT-S and LT-T modes by CH0-2), however after reset ...
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Non-Terminal Mode / LT-S Mode Similar as in LT-T mode, both DU and DD are inactive outside the selected 4-byte subscriber channel. Also the reset value for the active channel can be selected by pin strapping (in LT-S and LT-T ...
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Figure 58 IOM-2 Data Ports DU/DD in LT-S Mode (MODE0=1, MODE1=0) with Normal Layer 2 Direction (SPCR:SDL=1) Semiconductor Group Functional Description 123 PSB 2115 PSF 2115 11.97 ...
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Figure 59 IOM-2 Data Ports DU/DD in LT-S Mode (MODE0=1, MODE1=0) with Inversed Layer 2 Direction (SPCR:SDL=0) Semiconductor Group Functional Description 124 PSB 2115 PSF 2115 11.97 ...
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Microprocessor Access to B and IC Channels In IOM-2 terminal mode (TE mode, MODE0=0) the microprocessor can access the B and IC (intercommunication) channels at the IOM-2 interface by reading the B1CR/B2CR or by reading and writing the C1R/C2R ...
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S/T Interface Layer-1 Functions Figure 60 Principle of B/IC Channel Access in IOM (a) SPCR:C C1 monitoring, IC monitoring S/T Interface Layer-1 Functions Figure 61 Access to B and IC Channels in IOM Semiconductor Group ...
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SPCR:C C1 monitoring, IC looping S/T Interface Layer-1 Functions (c) SPCR:C C1 access from/to S/T transmission of constant value to S/T S/T Interface Layer-1 Functions Semiconductor Group Functional Description ...
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SPCR:C C1 looping from/to S/T transmission of variable pattern to S/T S/T Interface Layer-1 Functions Semiconductor Group Functional Description Bx Bx CxR P µ ITS09641 128 PSB 2115 PSF 2115 R IOM -2 Interface ...
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MONITOR Channel Handling In IOM-2 mode, the MONITOR channel protocol is a handshake protocol used for high speed information exchange between the IPAC and other devices in MONITOR channel "0" or "1" (see figure 53). In the non-TE mode, ...
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The microprocessor may either enforce a "1" (idle setting the control bit MRC1 MXC1 "0" (MONITOR Control Register MOCR), or enable the control of these bits internally by the IPAC according to ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 63 MONITOR Channel Protocol (IOM Semiconductor Group ...
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Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a "0" in the MONITOR Channel Active MAC status bit. After having written the ...
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Handshake Procedure Structure The structure of the monitor channel is 8 bit wide, located at bit position 16-23 in every time slot (assuming that the first bit in a time slot is located at bit position 0). Monitor messages ...
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R1/2: Monitor response 1. and 2. byte R IOM -2 Frame No Mon. Data Mon. Data DD Figure 64 Handshake Protocol with a 2-Byte Monitor Message/Response Idle State After the bits MR and ...
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The response of the IPAC will always be sent immediately after the 2. byte has been received and acknowledged. 5. After both monitor data bytes have been transferred to the IPAC, the controller transmits “End of Message” (EOM) by setting ...
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R IOM - Figure 65 Abortion of Monitor Channel Transmission 2.7.4.2 Monitor Procedure Timeout (TOD) The IPAC can operate with or without the “Monitor Timeout Procedure”. The TOD bit in the SM/CI (Timeout Disable) controls the timeout function. ...
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MON-1, MON-2 Commands (S/Q Channel Access) Function: MON-1 and MON-2 commands provide access to the IPAC internal S/Q registers. MON1 controls the S channel on the S-interface. In order to synchronize onto multiframing pulses (TE, LT-T modes) and issue ...
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Non-Auto Mode In non-auto mode only MON-1 functions to access the S MON-2 messages (for non-auto mode monitor messages are only released after new data has been received. In this mode traffic on the IOM monitor channel ...
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C/I-Channel Handling The Command/Indication channel carries real-time status information between the IPAC and another device connected to the IOM. 1) One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the layer-2 parts of the ...
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D-Channel Telemetry/ Packet Communication B-Channel Voice/Data Communication with D-Channel Signaling E-Channel IVD LAN Application B-Channel Voice/Data Communication with D-Channel Signaling Figure 66 Applications of TIC Bus in IOM Semiconductor Group R µ P IOM -2 ICC (7) ICC (2) DCL ...
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TIC Bus Access In IOM-2 interface mode the TIC bus capability is only available in TE mode. The arbitration mechanism implemented in the last octet of IOM channel 2 of the IOM-2 interface allows the access of external communication ...
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After a successful bus access, the IPAC is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. If none of the ...
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Auxiliary Interface 2.8.1 Mode Dependent Functions The AUX interface provides for various functions, which depend on the operation mode (TE, LT-T or LT-S mode) selected by pins MODE0 and MODE1/EAW (see table 15). After reset all pins except DRQTA ...
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Figure 69 Input/Output Characteristic of AUX Pins INT0, INT1 (all modes), INT1/SGOUT (LT-T mode) For all modes two pins can be used as programmable I/O with optional interrupt input capability (default after reset, i.e. both interrupts masked). The INT0/1 pins ...
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CH0, CH1, CH2 In linecard mode one FSC frame is a multiplex of eight IOM-2 channels, each of them consisting of B1-, B2-, MONITOR-, D- and C/I-channel and MR- and MX-bits LT-T and LT-S mode one of eight ...
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PCM Interface In LT-S and LT-T mode the IPAC provides a PCM interface (PCFG:PLD=0, default) that can be disabled (PCFG:PLD=1), so that the PCM pins can be used as general I/O pins (see previous chapter 2.8.1). 2.8.2.1 PCM Lines ...
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BCL Bit Clock (single rate): (FBOUT) For peripheral devices supporting single rate bit clock, the clock signal is provided at FBOUT derived from SCLK (LT-T mode) or from a system clock (LT-S mode internal divider (division ...
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Similar as on the IOM-2 interface, PCM data is written to PCMOUT with the first rising edge of DCL and latched in from PCMIN with the second falling edge of DCL (see figure 71). BCL is derived from the DCL ...
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The PCM interface can be used to build a connection between non IOM-2 compatible voice/data controllers and the IOM-2 interface in order to transfer B-channel data from/ to the external device. Receive data on the DD line can be mapped ...
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PCM *) Registers for timeslot programming. Figure 73 Data Path Switching 2.8.2.2 Clock Generation In LT-T mode a 1.536 MHz clock synchronous to the S interface is provided via pin SCLK, which can be connected to the DCL input and ...
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Therefore in multiline applications where two or three IPACs are connected across one IOM-2 interface, one IPAC may generate the FSC signal for all IPACs, while another one generates the BCL, if necessary, for peripheral devices (figure 75). Controller Figure ...
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Switching of Timeslots Figure 76 shows as an example, the switching of timeslots from the PCM lines to the data upstream and data downstream lines of IOM-2 channel B1. The datapath switching of channel B2 to the PCM interface ...
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PCM Transmit Line - PCMOUT By default the B-channel from the DD line (POTA1/2:DUDD=0) is connected to the PCM transmit line PCMOUT, so 8-bit data which is received by the IPAC from the S interface on DD (LT-T mode), is ...
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Oscillator Circuit The IPAC derives its system clocks from an external clock connected to XTAL1 (while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and XTAL2. At pin C768 a buffered 7.68 MHz output ...
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Operational Description 3.1 RESET After a reset the IPAC idle state and its registers are loaded with specific values. B-Channel registers The B-Channel related registers are located in the address range 00h - 73h. Their reset ...
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D-Channel registers The D-Channel registers are located in the address range 80h - BAh. The important reset values are summarized in table 18. Table 18 RESET Values for D-Channel Registers Register Value after Reset (hex) ISTAD 00 MASKD 00 EXIRD ...
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General IPAC registers The IPAC registers for general functions are located in the address range C0h - CCh. The reset values are summarized in table 18. Table 19 RESET Values for General IPAC Registers Register Value after Reset (hex) CONF ...
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Initialization After reset the CPU has to write a minimum set of registers and an optionally set dependent on the required features and operating modes. The CPU may switch the IPAC between power-up and power-down mode, which has no ...
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Table 21 User Demand Registers User Demand RFS Interrupt Provided Selective Interrupts Should be Masked DMA Controlled Data Transfer Receive Length Check Feature Extended (modulo 128) Counting D-Channel registers Register Bit SPCR SPU SDL SPM TLP C2C1-0 C1C1-0 MODED DIM2-0 ...
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Register Bit CIX0 RSS STCR TSF TBA2-0 TIMR CNT VALUE XAD1 XAD2 SAPI1/2 TEI1/2 Semiconductor Group Effect Hardware reset generated by either subscriber/exchange awake or watchdog timer Terminal specific function enable TIC bus address N1 and T1 in internal timer ...
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General IPAC registers Register Bit CONF ODS IOF IDH CFS AMP TEM PDS SGO PCFG PLD CSL2-0 FBS ACL LED PITA1/2 ENA DUDD TNRX Semiconductor Group Effect DU/DD output driver selection (open drain or push pull) IOM interface off or ...
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Register Bit POTA1/2 ENA DUDD TNTX SCFG PRI TLEN TSLT TIMR2 TMD CNT ACFG OD7-2 EL1,0 AOE OE7-2 Semiconductor Group Effect Enable PCMOUT channel Map data on DU/DD Timeslot number select Priority selection for IOM-2 D-channel priority handler Timeslot length ...
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Interrupt Structure and Logic Special events in the IPAC are indicated by means of a single interrupt output, which requests the host to read status information from the IPAC or transfer data from/to the IPAC. Since only one INT ...
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Two interrupt indications can be read directly from the ISTA register and another six interrupt indications from separate interrupt status registers and extended interrupt registers for the B-channels (ISTAB, EXIRB, each for B-Channel A and B) and the D- channel ...
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B-Channel Interrupts The B-Channel related interrupt sources can be logically grouped into – receive interrupts, – transmit interrupts and – special condition interrupts. Each interrupt indication of the ISTAB registers can be selectively masked by setting the respective bit ...
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Table 23 Transmit Interrupts XPR Transmit Pool Ready (ISTAB) XMR Transmit Message Repeat (EXIRB) XDU Transmit Data Underrun (EXIRB) Semiconductor Group Activated whenever a 64-byte FIFO pool is empty and accessible to the CPU, i.e. – following a XRES command ...
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D-Channel Interrupts The cause of an interrupt related to the D-Channel is determined by the microprocessor by reading the Interrupt Status Register ISTAD and the Extended Interrupt Status Register EXIRD. A read of the ISTAD register clears all bits ...
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Table 24 Interrupts from D-Channel HDLC Controller Mnemonic Register Meaning Layer-2 Receive RPF ISTAD Receive Pool Full. Request to read received octets of an uncompleted HDLC frame from RFIFOD. RME ISTAD Receive Message End. Request to read received octets of ...
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Table 24 Interrupts from D-Channel HDLC Controller (cont’d) Mnemonic Register Meaning XMR EXIRD Transmit Message Repeat. Frame must be repeated because of a transmission error (all HDLC message transfer modes received negative acknowledgment (auto mode only) from peer ...
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Figure 79 shows the CIC and MOS interrupt logic. CIC Interrupt Logic A CIC interrupt may originate – from a change in received C/I channel (0) code (CIC0) or (in the case of IOM-2 terminal mode only) – from a ...
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MOS Interrupt Logic In the case of IOM-2 non-terminal timing modes only one MONITOR channel is handled and MOR1 and MOX1 are unused. The interrupt logic is different for MONITOR channel 0 and channel 1: • MONITOR channel 0 The ...
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Figure 79 a) CIC Interrupt Structure b) MOS Interrupt Structure Semiconductor Group Operational Description 172 PSB 2115 PSF 2115 11.97 ...
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Auxiliary Interface Interrupts from external devices can be indicated in the Interrupt Status Register (ISTA) of the IPAC. The auxiliary pins AUX6 and 7 can be configured as general I/O pins and as inputs they can generate a maskable ...
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B-Channel Data Transfer Initially, the CPU should bring the transmitter and receiver to a defined state by issuing a XRES (transmitter reset) and RHR (receiver reset) command via the CMDRB register. If data reception should be performed, the receiver ...
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The data transmission sequence, from the CPU’s point of view, is outlined in figure 80. Command XTF Figure 80 Interrupt Driven Data Transmission (Flow Diagram) Semiconductor Group START Transmit N Pool Ready ? Y Write Data ( Bytes) ...
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The activities at both serial and CPU interface during frame transmission (supposed frame length = 140 bytes) is shown in figure 81. Serial Interface IPAC CPU ... Interface WR XTF 64 Bytes Figure 81 Interrupt Driven Transmission Sequence Example Semiconductor ...
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Back to Back Frames If two or more frames should be transmitted in a high speed sequence without interframe time fill, the transmission sequence according figure 82 has to be used. This means that the closing flag will be immediately ...
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The activities during frame transmission (supposed two frames, 36 bytes and 104 bytes) is shown in figure 83. Serial ITF Interface IPAC CPU ... Interface WR XTF 36 Bytes Figure 83 Continuous Frames Transmission Sequence Example DMA Mode Prior to ...
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The following figure gives an example of a DMA driven transmission sequence with a supposed frame length of 140 bytes, i.e. programmed transmit byte count (XCNT) equal 139 bytes. Serial Interface IPAC CPU/DMA Interface WR; XTF XCNT = 139 Figure ...
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Data Reception Interrupt Mode Also 2 64 byte FIFO buffers (receive pools) are provided for each channel in receive direction. There are two different interrupt indications concerned with the reception of data: • RPF (Receive Pool Full) interrupt, indicating ...
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The following figure gives an example of an interrupt controlled reception sequence, supposed that a long frame (132 bytes) followed by two short frames (12 bytes each) are received. Receive Frame 1 (132 Bytes Serial Interface IPAC CPU ...
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RFIFOB Contents DMA Request (No. of bytes) (No. of Bytes Note: All available status informations after RME are summarized in ...
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D-Channel Data Transfer 3.5.1 HDLC Frame Transmission After the XFIFOD status has been checked by polling the Transmit FIFO Write Enable (XFW) bit or after a Transmit Pool Ready (XPR) interrupt bytes may be entered in ...
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The HDLC controller will request another data block by an XPR interrupt if there are no more than 32 bytes in XFIFOD and the frame close command bit (Transmit Message End XME) has not been set. To this the microcontroller ...
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HDLC Frame Reception Assuming a normal running communication link (layer 1 activated, layer 2 link established), figure 88 illustrates the transfer frame. The transmitter is shown on the left and the receiver on the right, with ...
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Address Flag High Auto-Mode SAP1,SAP2 (U and I frames) FE,FC (Note 1) Non-Auto SAP1,SAP2 Mode FE,FC (Note 1) Transparent SAPR Mode 1 Transparent Mode 2 Transparent SAP1,SAP2 Mode 3 FE,FC Description of Symbols: Figure 89 Receive Data Flow Note 1: ...
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A frame longer than 32 bytes is transferred to the microcontroller in blocks of 32 bytes plus one remainder of length bytes. The reception of a 32-byte block is reported by a Receive Pool Full (RPF) interrupt ...
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Control of Layer-1 3.6.1 Activation/Deactivation of IOM In LT-T and LT-S applications the IOM interface should be kept active, i.e. the clock DCL and the frame sync FSC (inputs) should always be supplied by the system applications ...
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R IOM -2 FSC DIU DIU DCL Figure 90 Deactivation of the IOM The clock pulses will be enabled again when the DU line is pulled low (bit SPU, SPCR register) i.e. the C/I command TIM ...
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SPU = 1 FSC DU DD FSC DU 0 DCL Figure 91 Activation of the IOM Semiconductor Group IOM -CH1 IOM -CH2 IOM -CH1 IOM -CH2 132 x DCL ...
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The IPAC supplies IOM timing signals as long as there is no DIU command in the C/I (C/I0) channel. If timing signals are no longer required and activation is not yet requested, this is indicated by programming DIU in the ...
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It is essential to be able to interpret the state diagrams Interface INFO Figure 92 State Diagram Notation The following example illustrates the use of a state diagram with an extract of the TE state diagram. The ...
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As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “&” stands for a logical AND combination. An “or” indicates a logical OR combination. The sections following the state diagram contain detailed information ...
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TE/LT-T Modes State Diagram Pend. Act RSY X i4 F5/8 Unsynchron Synchronized Activated ...
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F3 Power Down DI ARL ARL Loop A Closed RSY ARL AIL Loop A Activated Note state “loop A activated” the internal signal, the external signal is I0. Figure 94 ...
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TE/LT-T Modes Transition Criteria The transition criteria used by the IPAC are described in the following sections. They are grouped into: – C/I commands – Pin states – Events related to the S/T-interface C/I Commands AR8 Activation Request with ...
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Pin States Pin-RES Pin-Reset. Corresponds to a high level at pin RST. At power up, a reset pulse (RST high active) of minimum 2 DCL clock cycles should be applied to bring the IPAC to the state “reset”. After that ...
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C/I Indications Abbreviation Indication DR Deactivate Request RES Reset TM1 Test mode 1 TM2 Test mode 2 SLIP Slip detected (LT-T only) RSY Resynchronization during level detect PU Power up AR Activate request ARL Activate request loop CVR Far-end-code-violation After ...
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S/T-Interface Signals I0 INFO 0 I1 INFO 1 I3 INFO 3 It Pseudo-ternary pulses at 2 kHz frequency (alternating, TM1) Pseudo-ternary pulses at 96 kHz frequency (alternating, TM2) States TE/LT-T Mode F3 power down This is the deactivated state of ...
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F6 synchronized When the IPAC receives an activation signal (INFO 2), it responds with INFO 3 and waits for normal frames (INFO 4). F7 activated This is the normal active state with the layer 1 protocol activated in both directions. ...