PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 296

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Electrical Characteristics
Jitter
In TE mode, the timing extraction jitter of the IPAC conforms to CCITT Recommendation
I.430 (– 7% to + 7% of the S-interface bit period).
In the LT-S applications, the clock input FSC is used as reference clock to provide the
192-kHz clock for the S-line interface. In the case of a plesiochronous 7.68-MHz clock
generated by an oscillator, the clock FSC should have a jitter less than 100 ns peak-to-
peak. (In the case of a zero input jitter on FSC the IPAC generates at most 65 ns "self-
jitter" on the S interface.)
In the case of a synchronous (fixed divider ratio between XTAL1 and DCL) 7.68-MHz
clock (input XTAL1), the IPAC transfers the input jitter of XTAL1, DCL and FSC to the S
interface. The maximum jitter of the LT-S output is limited to 260 ns peak-to-peak
(CCITT I.430).
Description of the Transmit PLL (XPLL) of the IPAC
Function of the XPLL
The XPLL generates a 1.536-MHz clock synchronized to the FSC 8-kHz clock by
modification of the counter's divider ratio. The 1.536-MHz clock is then divided to
192 kHz and 8 kHz. The 8 kHz is used as the looped back clock and compared to the
FSC 8-kHz in the phase detector.
Jitter considerations in case of a synchronous 7.68-MHz clock
After the XPLL has locked once, no more tracking steps are performed because there is
a fixed divider ratio of 960 between 7.68 MHz and FSC. Therefore the input jitter at FSC
and 7.68 MHz is transferred transparently to the S/T interface (192 kHz).
Jitter considerations in case of a plesiochronous 7.68-MHz clock (crystal)
Each tracking step of the XPLL produces an output jitter of 130 ns pp. In case of non-
zero input jitter at DCL, this input jitter is increased by 130 ns pp. That means that the
output jitter will not exceed 130 ns pp.
Semiconductor Group
296
11.97