PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 111

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Timer 2 can be used as a general purpose timer, similar to the ’External Timer Mode’ of
Timer 1. The host can configure a timer interrupt to the host which is indicated in
ISTAD:TIN2. If TIMR2:TMD=0 the timer is operating in count down mode, i.e. an
interrupt is only generated once after the programmed timer length. A periodic interrupt
is generated if TIMR2:TMD=1.
The timer length (for count down timer) or the timer period (for periodic timer),
respectively, can be configured to a value between 1 - 63 ms (TIMR2:CNT). If CNT=0
the timer function is disabled (see figure 49).
Figure 49
Semiconductor Group
an ’RNR’ S-frame has been received. A timer interrupt (ISTAD:TIN) is generated
after the last retry. The procedure is stopped when either a TIN interrupt is
generated or the TIMR1 register is written or when a positive or negative
acknowledgement is received.
CNT can have any value up to 6, with CNT=7 the number of retries is unlimited.
A detailed description for the use of the internal timer mode is provided with the
automode description (see chapter 2.2.1.3).
Note: The time period T1 is determined by the parameter VALUE (chapter 4.3.8).
2. External Timer Mode (MODED:TMD=0)
In the external mode the host controls the timer by setting bit CMDRD:STI to start
the timer and by writting register TIMR1 to stop the timer.
After time period T2 an interrupt (ISTAD:TIN) is generated continuously
(if CNT=7) or once (if CNT<7). Two time periods T2 are defined for normal mode
(SPCR:TLP=0) and for test mode (SPCR:TLP=1), i.e when test loop is activated.
Timer 2 Register
111
Functional Description
PSB 2115
PSF 2115
11.97