PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 104

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
2.6.5
To support efficient data exchange between system memory and the FIFOs an
additional DMA-interface is provided. The FIFOs have separate DMA-request lines for
each direction (DRQRA/B for Receive FIFO, DRQTA/B for Transmit FIFO) and a
common DMA-acknowledge input for receive and transmit direction (DACKA/B). The
DMA-controller has to operate in the level triggered, demand transfer mode. If the DMA-
controller provides a DMA-acknowledge signal, each bus cycle implicitly selects the top
of FIFO and neither address nor chip select is evaluated. If no DACKA/B signal is
supplied, normal read/write operations (providing addresses) must be performed
(memory to memory transfer).
In the paragraphs below the following abbreviations are used:
The IPAC activates the DRQT and DRQR-lines as long as data transfers are needed
from/to the specific FIFOs.
A special timing scheme is implemented to guarantee safe DMA-transfers regardless of
DMA-controller speed.
If in transmit direction a DMA-transfer of n bytes is necessary (n < 64 or the remainder
of a long message), the DRQT-pin is active up to the rising edge of WR of DMA-transfer
(n-1). If n
((k
further bytes to transfer (figure 41). When a fast DMA-controller is used (> 16 MHz),
byte n (or bytes k
this case pin DRQT is not activated any more up to the next block transfer (figure 40).
Figure 40
64) - 1). DRQT is activated again with the next rising edge of DACK, if there are
DMA Interface
of a long message or n = k
64 the same behavior applies additionally to transfers 63, 127, …,
Timing Diagram for DMA-Transfers (fast) Transmit (n < 64, remainder
64) will be transferred before DRQT is deactivated from the IPAC. In
DRQR =
DRQT =
DACK =
DRQRA or DRQRB
DRQTA or DRQTB
DACKA or DACKB
104
64)
Functional Description
PSB 2115
PSF 2115
11.97