PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 33

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.1.2
Characteristics: address recognition high byte
Only the high byte of a 2-byte address field will be compared. The whole frame except
the first address byte will be stored in RFIFOB. RAL1 contains the second and RHCRB
the third byte following the opening flag.
2.1.3
Characteristics: no address recognition
No address recognition is performed and each frame will be stored in the RFIFOB. RAL1
contains the first and RHCRB the second byte following the opening flag.
2.1.4
Characteristics: fully transparent
In extended transparent modes, fully transparent data transmission/reception without
HDLC framing is performed, i.e. without FLAG generation/recognition, CRC generation/
check, bit-stuffing mechanism. This allows user specific protocol variations or the usage
of Character Oriented Protocols (such as IBM BISYNC).
Data transmission is always performed out of the XFIFOB. In extended transparent
mode 0 (ADM = 0), data reception is done via the RAL1 register, which always contains
the actual data byte assembled at the DD pin. In extended transparent mode 1 (ADM =
1), the receive data are additionally shifted into the RFIFOB.
Also refer to chapter 2.1.8 and 2.1.9.
Semiconductor Group
Transparent Mode 1 (MODEB: MDS1, MDS0, ADM = 101)
Transparent Mode 0 (MODEB: MDS1, MDS0, ADM = 100)
Extended Transparent Modes 0, 1 (MODEB: MDS1, MDS0 = 11)
33
Functional Description
PSB 2115
PSF 2115
11.97