PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 185

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
3.5.2
Assuming a normal running communication link (layer 1 activated, layer 2 link
established), figure 88 illustrates the transfer of an I frame. The transmitter is shown on
the left and the receiver on the right, with the interaction between the microcontroller
system and the IPAC in terms of interrupt and command stimuli.
When the frame (excluding the CRC field) is not longer than 32 bytes, the whole frame
is transferred in one block. The reception of the frame is reported via the Receive
Message End (RME) interrupt. The number of bytes stored in RFIFOD can be read out
from RBCLD. The Receive Status Register (RSTAD) includes information about the
frame, such as frame aborted yes/no or CRC valid yes/no and, if complete or partial
address recognition is selected, the identification of the frame address.
Depending on the HDLC message transfer mode, the address and control field of the
frame can be read from auxiliary registers (SAPR and RHCRD), as shown in figure 89.
Figure 88
*) In Auto Mode the "RR" Response will be Transmitted Autonomously
System
µ
C-
HDLC Frame Reception
change)
: = Data Transfer
Transmission of an I Frame in the D Channel (Subscriber to Ex-
IPAC
LAPD Link
185
IPAC
Operational Description
System
PSB 2115
PSF 2115
ITD09654
µ
C-
11.97