PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 112

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
2.6.8
The host can issue a reset command to the IPAC which has the same functionality as a
hardware reset. In register C9h bit POTA2:SRES (Software Reset) is used to release the
reset which has only effect on the internal functional blocks of the IPAC. The reset pin
RES (pin 34) is not activated.
The duration of the reset is controlled by the host, i.e. SRES is set to ’1’ by the host and
the reset state is active until SRES is set to ’0’. The host must ensure the required reset
timing of the IPAC which is 4 ms.
Figure 50
Software Reset
Reset Timing
SRES=1
SRES=0
Activate
Reset
min. 4 ms
Host
IPAC
112
Deactivate
Reset
2115_31
Functional Description
PSB 2115
PSF 2115
11.97