PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 147

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
The frame sync signal FSC and the data clock DCL which are used on the IOM-2
interface also serve as the reference clocks on the PCM interface.
The rising edge of FSC marks the beginning of a new frame that consists of several
timeslots each of which is 8 bits long (see figure 70). Depending on the frequency of the
DCL clock the host can select one of up to 32 possible timeslots (DCL = 4.096 MHz) on
the PCM interface from which B-channel data is read from (PCMIN) and written to
(PCMOUT).
Figure 70
BCL
(FBOUT)
FSC
(FBOUT)
Bit Clock (single rate):
For peripheral devices supporting single rate bit clock, the clock signal
is provided at FBOUT. It is derived from SCLK (LT-T mode) or from a
system clock (LT-S mode) by an internal divider (division by 2). See
chapter 2.8.2.2.
Frame Sync:
The frame sync signal is multiplexed with BCL (see above) and output
at FBOUT. It is derived from SCLK (LT-T mode) or from a system clock
(LT-S mode) by an internal divider (division by 192). See chapter
2.8.2.2.
PCM Frame Alignment
147
Functional Description
PSB 2115
PSF 2115
11.97