PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 170

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Operational Description
Figure 79 shows the CIC and MOS interrupt logic.
CIC Interrupt Logic
A CIC interrupt may originate
– from a change in received C/I channel (0) code (CIC0)
or (in the case of IOM-2 terminal mode only)
– from a change in received C/I channel 1 code (CIC 1).
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E (ADF1 register). In this case the
occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
But in the case of a code change, the new code is not loaded until the previous contents
have been read. When this is done and a second code change has already occurred, a
new interrupt is immediately generated and the new code replaces the previous one in
the register. The code registers are buffered with a FIFO size of two. Thus, if several
consecutive codes are detected, only the first and the last code is obtained at the first
and second register read, respectively.
Semiconductor Group
170
11.97