PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 105

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

transfer ((k
are further bytes to transfer (figure 43). When a fast DMA-controller is used (> 16 MHz),
byte n (or bytes k
However, if 4, 8, 16, 32 or 64 bytes have to be transferred (only these discrete values
are possible in receive direction), DRQR is deactivated with the falling edge of RD
Figure 41
In receive direction the behavior of pin DRQR is implemented correspondingly. If k
bytes are transferred, pin DRQR is deactivated with the rising edge of RD of DMA-
(figure 44).
Figure 42
Semiconductor Group
der of a long message or n = k
64)
Timing Diagram for DMA-Transfers (slow) Transmit (n < 64, remain-
Timing Diagram for DMA-Transfer (fast) Receive (n = k
1) and it is activated again with the next rising edge of DACK, if there
64) will be transferred immediately (figure 42).
105
64)
Functional Description
64)
PSB 2115
PSF 2115
11.97
64