PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 156

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

SPCR
CIR0
CIX0
STCR
ADF1
D-Channel registers
The D-Channel registers are located in the address range 80h - BAh. The important
reset values are summarized in table 18.
Table 18 RESET Values for D-Channel Registers
Register
ISTAD
MASKD
EXIRD
STARD
CMDRD
MODED
RBCLD
RBCHD
Semiconductor Group
00
00
Value after
Reset (hex)
00
00
48
00
00
00
XXX00000
00
7C
3F
00
2
Meaning
– no interrupts
– all interrupts enabled
– no interrupts
– XFIFOD is ready to be written to
– RFIFOD is ready to receive at least 16 octets of a
– no command
– auto mode
– 1-octet address field
– external timer mode
– receiver inactive
– no frame bytes received
– DU pin = “High”
– IOM interface test loop deactivated
– another device occupies the D and C/I channels
– received C/I code = “1111”
– no C/I code change
– TIC bus is not requested for transmitting a C/I code
– transmitted C/I code = “1111”
– terminal specific functions disabled
– TIC bus address = “0000”
– no synchronous transfer
– inter-frame time fill = continuous “1”
new message
156
Operational Description
PSB 2115
PSF 2115
11.97