PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 189

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
Figure 90
The clock pulses will be enabled again when the DU line is pulled low (bit SPU, SPCR
register) i.e. the C/I command TIM = "0000" is received by layer 1, or when a non-zero
level on the S-line interface is detected. The clocks are turned on after approximately 0.2
to 4 ms depending on the capacitances on XTAL 1/2.
DCL is activated such that its first rising edge occurs with the beginning of the bit
following the C/I (C/I0) channel.
After the clocks have been enabled this is indicated by the PU code in the C/I channel
and, consequently, by a CIC interrupt. The DU line may be released by resetting the
Software Power Up bit SPCR:SPU=0, and the C/I code written to CIX0 before (e.g. TIM
or AR8) is output on DU.
IOM -2
FSC
DU
DD
DCL
R
DIU
DR
Deactivation of the IOM
DIU
DR
DIU
DR
DIU
DR
®
DIU
DR
Interface
B1
189
DIU
DID
D
B2
DID
DIU
MONO
CIO
DID
DIU
Operational Description
D
ITD09655
CIO
DIU
DID
IOM -2
Deactivated
PSB 2115
PSF 2115
R
11.97